diff --git a/vm-virtio/src/transport/pci_common_config.rs b/vm-virtio/src/transport/pci_common_config.rs
index a5c837747..eb9f3bcf7 100644
--- a/vm-virtio/src/transport/pci_common_config.rs
+++ b/vm-virtio/src/transport/pci_common_config.rs
@@ -302,41 +302,41 @@ mod tests {
             msix_config: Arc::new(AtomicU16::new(0)),
         };
 
-        let dev = &mut DummyDevice(0) as &mut dyn VirtioDevice;
+        let dev = Arc::new(Mutex::new(DummyDevice(0)));
         let mut queues = Vec::new();
 
         // Can set all bits of driver_status.
-        regs.write(0x14, &[0x55], &mut queues, dev);
+        regs.write(0x14, &[0x55], &mut queues, dev.clone());
         let mut read_back = vec![0x00];
-        regs.read(0x14, &mut read_back, &mut queues, dev);
+        regs.read(0x14, &mut read_back, &mut queues, dev.clone());
         assert_eq!(read_back[0], 0x55);
 
         // The config generation register is read only.
-        regs.write(0x15, &[0xaa], &mut queues, dev);
+        regs.write(0x15, &[0xaa], &mut queues, dev.clone());
         let mut read_back = vec![0x00];
-        regs.read(0x15, &mut read_back, &mut queues, dev);
+        regs.read(0x15, &mut read_back, &mut queues, dev.clone());
         assert_eq!(read_back[0], 0x55);
 
         // Device features is read-only and passed through from the device.
-        regs.write(0x04, &[0, 0, 0, 0], &mut queues, dev);
+        regs.write(0x04, &[0, 0, 0, 0], &mut queues, dev.clone());
         let mut read_back = vec![0, 0, 0, 0];
-        regs.read(0x04, &mut read_back, &mut queues, dev);
+        regs.read(0x04, &mut read_back, &mut queues, dev.clone());
         assert_eq!(LittleEndian::read_u32(&read_back), DUMMY_FEATURES as u32);
 
         // Feature select registers are read/write.
-        regs.write(0x00, &[1, 2, 3, 4], &mut queues, dev);
+        regs.write(0x00, &[1, 2, 3, 4], &mut queues, dev.clone());
         let mut read_back = vec![0, 0, 0, 0];
-        regs.read(0x00, &mut read_back, &mut queues, dev);
+        regs.read(0x00, &mut read_back, &mut queues, dev.clone());
         assert_eq!(LittleEndian::read_u32(&read_back), 0x0403_0201);
-        regs.write(0x08, &[1, 2, 3, 4], &mut queues, dev);
+        regs.write(0x08, &[1, 2, 3, 4], &mut queues, dev.clone());
         let mut read_back = vec![0, 0, 0, 0];
-        regs.read(0x08, &mut read_back, &mut queues, dev);
+        regs.read(0x08, &mut read_back, &mut queues, dev.clone());
         assert_eq!(LittleEndian::read_u32(&read_back), 0x0403_0201);
 
         // 'queue_select' can be read and written.
-        regs.write(0x16, &[0xaa, 0x55], &mut queues, dev);
+        regs.write(0x16, &[0xaa, 0x55], &mut queues, dev.clone());
         let mut read_back = vec![0x00, 0x00];
-        regs.read(0x16, &mut read_back, &mut queues, dev);
+        regs.read(0x16, &mut read_back, &mut queues, dev.clone());
         assert_eq!(read_back[0], 0xaa);
         assert_eq!(read_back[1], 0x55);
     }