misc: Fix spelling issues

Misspellings were identified by:
  https://github.com/marketplace/actions/check-spelling

* Initial corrections based on forbidden patterns from the action
* Additional corrections by Google Chrome auto-suggest
* Some manual corrections
* Adding markdown bullets to readme credits section

Signed-off-by: Josh Soref <2119212+jsoref@users.noreply.github.com>

hypervisor/src/arch/x86/emulator/mod.rs

@@ -135,7 +135,7 @@ pub trait CpuStateManager: Clone {
                     .checked_add(segment_register.base)
                     .ok_or_else(|| {
                         PlatformError::InvalidAddress(anyhow!(
-                            "Logical address {:#x} can not be linearized with segment {:#x?}",
+                            "Logical address {:#x} cannot be linearized with segment {:#x?}",
                             logical_addr,
                             segment_register
                         ))
@@ -148,7 +148,7 @@ pub trait CpuStateManager: Clone {
                 // Must not write to a read-only segment.
                 if segment_type_ro(segment_type) && write {
                     return Err(PlatformError::InvalidAddress(anyhow!(
-                        "Can not write to a read-only segment"
+                        "Cannot write to a read-only segment"
                     )));
                 }
 

hypervisor/src/hypervisor.rs

@@ -166,7 +166,7 @@ pub trait Hypervisor: Send + Sync {
                 CpuVendor::AMD
             } else {
                 // Not known yet, the corresponding manufacturer manual should contain the
-                // necesssary info. See also https://wiki.osdev.org/CPUID#CPU_Vendor_ID_String
+                // necessary info. See also https://wiki.osdev.org/CPUID#CPU_Vendor_ID_String
                 CpuVendor::default()
             }
         }

hypervisor/src/kvm/aarch64/gic/redist_regs.rs

@@ -46,7 +46,7 @@ const KVM_ARM64_SYSREG_MPIDR_EL1: u64 = KVM_REG_ARM64
     | (((5_u64) << KVM_REG_ARM64_SYSREG_OP2_SHIFT) & KVM_REG_ARM64_SYSREG_OP2_MASK as u64);
 
 /// This is how we represent the registers of a distributor.
-/// It is relrvant their offset from the base address of the
+/// It is relevant their offset from the base address of the
 /// distributor.
 /// Each register has a different number
 /// of bits_per_irq and is therefore variable length.

hypervisor/src/kvm/mod.rs

@@ -535,9 +535,9 @@ impl vm::Vm for KvmVm {
 
                 if self.check_extension(crate::kvm::Cap::MsiDevid) {
                     // On AArch64, there is limitation on the range of the 'devid',
-                    // it can not be greater than 65536 (the max of u16).
+                    // it cannot be greater than 65536 (the max of u16).
                     //
-                    // BDF can not be used directly, because 'segment' is in high
+                    // BDF cannot be used directly, because 'segment' is in high
                     // 16 bits. The layout of the u32 BDF is:
                     // |---- 16 bits ----|-- 8 bits --|-- 5 bits --|-- 3 bits --|
                     // |      segment    |     bus    |   device   |  function  |
@@ -1505,7 +1505,7 @@ impl cpu::Vcpu for KvmVcpu {
 
     #[cfg(target_arch = "x86_64")]
     ///
-    /// Set the floating point state (FPU) of a vCPU using the `KVM_SET_FPU` ioct.
+    /// Set the floating point state (FPU) of a vCPU using the `KVM_SET_FPU` ioctl.
     ///
     fn set_fpu(&self, fpu: &FpuState) -> cpu::Result<()> {
         let fpu: kvm_bindings::kvm_fpu = (*fpu).clone().into();
@@ -1986,7 +1986,7 @@ impl cpu::Vcpu for KvmVcpu {
     /// SREGS saves/restores a pending interrupt, similar to what
     /// VCPU_EVENTS also does.
     ///
-    /// GET_MSRS requires a pre-populated data structure to do something
+    /// GET_MSRS requires a prepopulated data structure to do something
     /// meaningful. For SET_MSRS it will then contain good data.
     ///
     /// # Example

hypervisor/src/mshv/mod.rs

@@ -1329,7 +1329,7 @@ impl cpu::Vcpu for MshvVcpu {
         self.set_fpu(&state.fpu)?;
         self.set_xcrs(&state.xcrs)?;
         // These registers are global and needed to be set only for first VCPU
-        // as Microsoft Hypervisor allows setting this regsier for only one VCPU
+        // as Microsoft Hypervisor allows setting this register for only one VCPU
         if self.vp_index == 0 {
             self.fd
                 .set_misc_regs(&state.misc)

hypervisor/src/vm.rs

@@ -190,7 +190,7 @@ pub enum HypervisorVmError {
     /// Assert virtual interrupt error
     ///
     #[error("Failed to assert virtual Interrupt: {0}")]
-    AsserttVirtualInterrupt(#[source] anyhow::Error),
+    AssertVirtualInterrupt(#[source] anyhow::Error),
 
     #[cfg(feature = "sev_snp")]
     ///