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hypervisor: Don't create temporary vector for boot MSRs

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The MSRs are constant at boot time so rather than creating a vector in
the boot_msr_entries() method instead reaturn a reference to static MSR
array data.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
This commit is contained in:
Rob Bradford 2025-11-26 12:28:05 +00:00
parent a91235dab1
commit 4abebc9e56
5 changed files with 7 additions and 9 deletions
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2
arch/src/x86_64/regs.rs
View file

@ -82,7 +82,7 @@ pub fn setup_fpu(vcpu: &dyn hypervisor::Vcpu) -> Result<()> {
///
/// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
pub fn setup_msrs(vcpu: &dyn hypervisor::Vcpu) -> Result<()> {
vcpu.set_msrs(&vcpu.boot_msr_entries())
vcpu.set_msrs(vcpu.boot_msr_entries())
.map_err(Error::SetModelSpecificRegisters)?;
Ok(())

2
hypervisor/src/cpu.rs
View file

@ -558,7 +558,7 @@ pub trait Vcpu: Send + Sync {
///
/// Return the list of initial MSR entries for a VCPU
///
fn boot_msr_entries(&self) -> Vec<MsrEntry>;
fn boot_msr_entries(&self) -> &'static [MsrEntry];
#[cfg(target_arch = "x86_64")]
///

5
hypervisor/src/kvm/mod.rs
View file

@ -2732,10 +2732,10 @@ impl cpu::Vcpu for KvmVcpu {
///
/// Return the list of initial MSR entries for a VCPU
///
fn boot_msr_entries(&self) -> Vec<MsrEntry> {
fn boot_msr_entries(&self) -> &'static [MsrEntry] {
use crate::arch::x86::{MTRR_ENABLE, MTRR_MEM_TYPE_WB, msr_index};
[
&[
msr!(msr_index::MSR_IA32_SYSENTER_CS),
msr!(msr_index::MSR_IA32_SYSENTER_ESP),
msr!(msr_index::MSR_IA32_SYSENTER_EIP),
@ -2751,7 +2751,6 @@ impl cpu::Vcpu for KvmVcpu {
),
msr_data!(msr_index::MSR_MTRRdefType, MTRR_ENABLE | MTRR_MEM_TYPE_WB),
]
.to_vec()
}
#[cfg(target_arch = "aarch64")]

5
hypervisor/src/mshv/mod.rs
View file

@ -1449,10 +1449,10 @@ impl cpu::Vcpu for MshvVcpu {
///
/// Return the list of initial MSR entries for a VCPU
///
fn boot_msr_entries(&self) -> Vec<MsrEntry> {
fn boot_msr_entries(&self) -> &'static [MsrEntry] {
use crate::arch::x86::{MTRR_ENABLE, MTRR_MEM_TYPE_WB, msr_index};
[
&[
msr!(msr_index::MSR_IA32_SYSENTER_CS),
msr!(msr_index::MSR_IA32_SYSENTER_ESP),
msr!(msr_index::MSR_IA32_SYSENTER_EIP),
@ -1463,7 +1463,6 @@ impl cpu::Vcpu for MshvVcpu {
msr!(msr_index::MSR_SYSCALL_MASK),
msr_data!(msr_index::MSR_MTRRdefType, MTRR_ENABLE | MTRR_MEM_TYPE_WB),
]
.to_vec()
}
///

2
vmm/src/cpu.rs
View file

@ -3088,7 +3088,7 @@ mod unit_tests {
// tenth one (i.e the one with index msr_index::MSR_IA32_MISC_ENABLE has the data we
// expect.
let entry_vec = vcpu.boot_msr_entries();
assert_eq!(entry_vec.as_slice()[9], msrs.as_slice()[0]);
assert_eq!(entry_vec[9], msrs.as_slice()[0]);
}
#[test]