devices: Add fw_cfg device
Here we add the fw_cfg device as a legacy device to the device manager. It is guarded behind a fw_cfg flag in vmm at creation of the DeviceManager. In this cl we implement the fw_cfg device with one function (signature). Signed-off-by: Alex Orozco <alexorozco@google.com>
This commit is contained in:
Alex Orozco
Bo Chen
parent
5226ceb974
commit
777b7ee11e
11 changed files with 455 additions and 0 deletions
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@ -28,11 +28,16 @@ vm-memory = { workspace = true, features = [
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] }
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vm-migration = { path = "../vm-migration" }
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vmm-sys-util = { workspace = true }
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zerocopy = { version = "0.8.26", features = [
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"alloc",
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"derive",
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], optional = true }
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[target.'cfg(any(target_arch = "aarch64", target_arch = "riscv64"))'.dependencies]
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arch = { path = "../arch" }
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[features]
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default = []
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fw_cfg = ["zerocopy"]
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kvm = ["arch/kvm"]
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pvmemcontrol = []
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309
devices/src/legacy/fw_cfg.rs
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309
devices/src/legacy/fw_cfg.rs
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@ -0,0 +1,309 @@
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// Copyright 2025 Google LLC.
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//
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// SPDX-License-Identifier: Apache-2.0
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//
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/// Cloud Hypervisor implementation of Qemu's fw_cfg spec
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/// https://www.qemu.org/docs/master/specs/fw_cfg.html
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/// Linux kernel fw_cfg driver header
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/// https://github.com/torvalds/linux/blob/master/include/uapi/linux/qemu_fw_cfg.h
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/// Uploading files to the guest via fw_cfg is supported for all kernels 4.6+ w/ CONFIG_FW_CFG_SYSFS enabled
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/// https://cateee.net/lkddb/web-lkddb/FW_CFG_SYSFS.html
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/// No kernel requirement if above functionality is not required,
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/// only firmware must implement mechanism to interact with this fw_cfg device
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use std::{
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fs::File,
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io::Result,
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mem::size_of_val,
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os::unix::fs::FileExt,
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sync::{Arc, Barrier},
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};
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use vm_device::BusDevice;
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use vmm_sys_util::sock_ctrl_msg::IntoIovec;
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use zerocopy::{FromBytes, IntoBytes};
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#[cfg(target_arch = "x86_64")]
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const PORT_FW_CFG_SELECTOR: u64 = 0x510;
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#[cfg(target_arch = "x86_64")]
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const PORT_FW_CFG_DATA: u64 = 0x511;
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#[cfg(target_arch = "x86_64")]
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const PORT_FW_CFG_DMA_HI: u64 = 0x514;
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#[cfg(target_arch = "x86_64")]
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const PORT_FW_CFG_DMA_LO: u64 = 0x518;
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#[cfg(target_arch = "x86_64")]
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pub const PORT_FW_CFG_BASE: u64 = 0x510;
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#[cfg(target_arch = "x86_64")]
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pub const PORT_FW_CFG_WIDTH: u64 = 0xc;
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#[cfg(target_arch = "aarch64")]
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const PORT_FW_CFG_SELECTOR: u64 = 0x9030008;
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#[cfg(target_arch = "aarch64")]
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const PORT_FW_CFG_DATA: u64 = 0x9030000;
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#[cfg(target_arch = "aarch64")]
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const PORT_FW_CFG_DMA_HI: u64 = 0x9030010;
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#[cfg(target_arch = "aarch64")]
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const PORT_FW_CFG_DMA_LO: u64 = 0x9030014;
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#[cfg(target_arch = "aarch64")]
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pub const PORT_FW_CFG_BASE: u64 = 0x9030000;
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#[cfg(target_arch = "aarch64")]
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pub const PORT_FW_CFG_WIDTH: u64 = 0x10;
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const FW_CFG_SIGNATURE: u16 = 0x00;
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const FW_CFG_ID: u16 = 0x01;
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const FW_CFG_FILE_DIR: u16 = 0x19;
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const FW_CFG_KNOWN_ITEMS: usize = 0x20;
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pub const FW_CFG_FILE_FIRST: u16 = 0x20;
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pub const FW_CFG_DMA_SIGNATURE: [u8; 8] = *b"QEMU CFG";
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// Reserved (must be enabled)
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const FW_CFG_F_RESERVED: u8 = 1 << 0;
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// DMA Toggle Bit (enabled by default)
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const FW_CFG_F_DMA: u8 = 1 << 1;
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pub const FW_CFG_FEATURE: [u8; 4] = [FW_CFG_F_RESERVED | FW_CFG_F_DMA, 0, 0, 0];
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#[derive(Debug)]
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pub enum FwCfgContent {
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Bytes(Vec<u8>),
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Slice(&'static [u8]),
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File(u64, File),
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U32(u32),
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}
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impl Default for FwCfgContent {
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fn default() -> Self {
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FwCfgContent::Slice(&[])
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}
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}
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impl FwCfgContent {
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fn size(&self) -> Result<u32> {
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let ret = match self {
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FwCfgContent::Bytes(v) => v.len(),
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FwCfgContent::File(offset, f) => (f.metadata()?.len() - offset) as usize,
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FwCfgContent::Slice(s) => s.len(),
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FwCfgContent::U32(n) => size_of_val(n),
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};
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u32::try_from(ret).map_err(|_| std::io::ErrorKind::InvalidInput.into())
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}
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}
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#[derive(Debug, Default)]
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pub struct FwCfgItem {
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pub name: String,
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pub content: FwCfgContent,
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}
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/// https://www.qemu.org/docs/master/specs/fw_cfg.html
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#[derive(Debug, Default)]
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pub struct FwCfg {
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selector: u16,
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data_offset: u32,
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items: Vec<FwCfgItem>, // 0x20 and above
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known_items: [FwCfgContent; FW_CFG_KNOWN_ITEMS], // 0x0 to 0x19
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}
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#[repr(C)]
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#[derive(Debug, IntoBytes, FromBytes)]
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struct FwCfgFilesHeader {
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count_be: u32,
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}
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pub const FILE_NAME_SIZE: usize = 56;
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pub fn create_file_name(name: &str) -> [u8; FILE_NAME_SIZE] {
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let mut c_name = [0u8; FILE_NAME_SIZE];
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let c_len = std::cmp::min(FILE_NAME_SIZE - 1, name.len());
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c_name[0..c_len].copy_from_slice(&name.as_bytes()[0..c_len]);
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c_name
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}
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#[allow(dead_code)]
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#[repr(C, packed)]
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#[derive(Debug, IntoBytes, FromBytes, Clone, Copy)]
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struct BootE820Entry {
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addr: u64,
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size: u64,
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type_: u32,
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}
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#[repr(C)]
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#[derive(Debug, IntoBytes, FromBytes)]
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struct FwCfgFile {
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size_be: u32,
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select_be: u16,
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_reserved: u16,
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name: [u8; FILE_NAME_SIZE],
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}
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impl FwCfg {
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pub fn new() -> FwCfg {
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const DEFAULT_ITEM: FwCfgContent = FwCfgContent::Slice(&[]);
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let mut known_items = [DEFAULT_ITEM; FW_CFG_KNOWN_ITEMS];
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known_items[FW_CFG_SIGNATURE as usize] = FwCfgContent::Slice(&FW_CFG_DMA_SIGNATURE);
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known_items[FW_CFG_ID as usize] = FwCfgContent::Slice(&FW_CFG_FEATURE);
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let file_buf = Vec::from(FwCfgFilesHeader { count_be: 0 }.as_mut_bytes());
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known_items[FW_CFG_FILE_DIR as usize] = FwCfgContent::Bytes(file_buf);
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FwCfg {
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selector: 0,
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data_offset: 0,
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items: vec![],
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known_items,
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}
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}
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fn file_dir_mut(&mut self) -> &mut Vec<u8> {
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let FwCfgContent::Bytes(file_buf) = &mut self.known_items[FW_CFG_FILE_DIR as usize] else {
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unreachable!("fw_cfg: selector {FW_CFG_FILE_DIR:#x} should be FwCfgContent::Byte!")
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};
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file_buf
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}
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fn update_count(&mut self) {
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let mut header = FwCfgFilesHeader {
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count_be: (self.items.len() as u32).to_be(),
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};
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self.file_dir_mut()[0..4].copy_from_slice(header.as_mut_bytes());
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}
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pub fn add_item(&mut self, item: FwCfgItem) -> Result<()> {
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let index = self.items.len();
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let c_name = create_file_name(&item.name);
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let size = item.content.size()?;
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let mut cfg_file = FwCfgFile {
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size_be: size.to_be(),
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select_be: (FW_CFG_FILE_FIRST + index as u16).to_be(),
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_reserved: 0,
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name: c_name,
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};
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self.file_dir_mut()
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.extend_from_slice(cfg_file.as_mut_bytes());
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self.items.push(item);
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self.update_count();
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Ok(())
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}
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fn read_content(content: &FwCfgContent, offset: u32, data: &mut [u8], size: u32) -> Option<u8> {
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let start = offset as usize;
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let end = start + size as usize;
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match content {
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FwCfgContent::Bytes(b) => {
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if b.len() >= size as usize {
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data.copy_from_slice(&b[start..end]);
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}
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}
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FwCfgContent::Slice(s) => {
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if s.len() >= size as usize {
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data.copy_from_slice(&s[start..end]);
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}
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}
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FwCfgContent::File(o, f) => {
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f.read_exact_at(data, o + offset as u64).ok()?;
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}
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FwCfgContent::U32(n) => {
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let bytes = n.to_le_bytes();
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data.copy_from_slice(&bytes[start..end]);
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}
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};
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Some(size as u8)
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}
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fn read_data(&mut self, data: &mut [u8], size: u32) -> u8 {
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let ret = if let Some(content) = self.known_items.get(self.selector as usize) {
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Self::read_content(content, self.data_offset, data, size)
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} else if let Some(item) = self.items.get((self.selector - FW_CFG_FILE_FIRST) as usize) {
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Self::read_content(&item.content, self.data_offset, data, size)
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} else {
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error!("fw_cfg: selector {:#x} does not exist.", self.selector);
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None
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};
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if let Some(val) = ret {
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self.data_offset += size;
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val
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} else {
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0
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}
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}
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}
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impl BusDevice for FwCfg {
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fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
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let port = offset + PORT_FW_CFG_BASE;
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let size = data.len();
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match (port, size) {
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(PORT_FW_CFG_SELECTOR, _) => {
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error!("fw_cfg: selector register is write-only.");
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}
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(PORT_FW_CFG_DATA, _) => _ = self.read_data(data, size as u32),
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(PORT_FW_CFG_DMA_HI, 4) => {
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unimplemented!()
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}
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(PORT_FW_CFG_DMA_LO, 4) => {
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unimplemented!()
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}
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_ => {
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debug!("fw_cfg: read from unknown port {port:#x}: {size:#x} bytes and offset {offset:#x}.");
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}
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};
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}
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fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
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let port = offset + PORT_FW_CFG_BASE;
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let size = data.size();
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match (port, size) {
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(PORT_FW_CFG_SELECTOR, 2) => {
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let mut buf = [0u8; 2];
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buf[..size].copy_from_slice(&data[..size]);
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#[cfg(target_arch = "x86_64")]
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let val = u16::from_le_bytes(buf);
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#[cfg(target_arch = "aarch64")]
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let val = u16::from_be_bytes(buf);
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self.selector = val;
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self.data_offset = 0;
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}
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(PORT_FW_CFG_DATA, 1) => error!("fw_cfg: data register is read-only."),
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(PORT_FW_CFG_DMA_HI, 4) => {
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unimplemented!()
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}
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(PORT_FW_CFG_DMA_LO, 4) => {
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unimplemented!()
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}
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_ => debug!(
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"fw_cfg: write to unknown port {port:#x}: {size:#x} bytes and offset {offset:#x} ."
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),
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};
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None
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}
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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#[cfg(target_arch = "x86_64")]
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const SELECTOR_OFFSET: u64 = 0;
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#[cfg(target_arch = "aarch64")]
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const SELECTOR_OFFSET: u64 = 8;
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#[cfg(target_arch = "x86_64")]
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const DATA_OFFSET: u64 = 1;
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#[cfg(target_arch = "aarch64")]
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const DATA_OFFSET: u64 = 0;
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#[test]
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fn test_signature() {
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let mut fw_cfg = FwCfg::new();
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let mut data = vec![0u8];
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let mut sig_iter = FW_CFG_DMA_SIGNATURE.into_iter();
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fw_cfg.write(0, SELECTOR_OFFSET, &[FW_CFG_SIGNATURE as u8, 0]);
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loop {
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if let Some(char) = sig_iter.next() {
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fw_cfg.read(0, DATA_OFFSET, &mut data);
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assert_eq!(data[0], char);
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} else {
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return;
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}
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}
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}
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}
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@ -8,6 +8,8 @@
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mod cmos;
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#[cfg(target_arch = "x86_64")]
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mod debug_port;
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#[cfg(feature = "fw_cfg")]
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pub mod fw_cfg;
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#[cfg(target_arch = "x86_64")]
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mod fwdebug;
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#[cfg(target_arch = "aarch64")]
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@ -22,6 +24,8 @@ mod uart_pl011;
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pub use self::cmos::Cmos;
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#[cfg(target_arch = "x86_64")]
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pub use self::debug_port::DebugPort;
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#[cfg(feature = "fw_cfg")]
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pub use self::fw_cfg::FwCfg;
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#[cfg(target_arch = "x86_64")]
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pub use self::fwdebug::FwDebugDevice;
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#[cfg(target_arch = "aarch64")]
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