dsg/cloud-hypervisor
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

misc: clippy: add unnecessary_semicolon

Browse source 
Signed-off-by: Philipp Schuster <philipp.schuster@cyberus-technology.de>
On-behalf-of: SAP philipp.schuster@sap.com
This commit is contained in:
Philipp Schuster 2025-11-18 12:23:48 +01:00 • committed by Rob Bradford
parent 06390342a6
commit 7cb73e9e56
36 changed files with 72 additions and 73 deletions
Download patch file Download diff file Expand all files Collapse all files

2
pci/src/configuration.rs
View file

@ -593,7 +593,7 @@ impl PciConfiguration {
writable_bits[9] = 0xfff0_fff0; // Memory base and limit
writable_bits[15] = 0xffff_00ff; // Bridge control (r/w), interrupt line (r/w)
}
};
}
registers[11] = (u32::from(subsystem_id) << 16) | u32::from(subsystem_vendor_id);
(

6
pci/src/msix.rs
View file

@ -288,7 +288,7 @@ impl MsixConfig {
self.table_entries[index].vector_ctl = value;
}
_ => error!("invalid offset"),
};
}
debug!("MSI_W TABLE offset 0x{offset:x} data 0x{value:x}");
}
@ -304,12 +304,12 @@ impl MsixConfig {
self.table_entries[index].vector_ctl = (value >> 32) as u32;
}
_ => error!("invalid offset"),
};
}
debug!("MSI_W TABLE offset 0x{offset:x} data 0x{value:x}");
}
_ => error!("invalid data length"),
};
}
let table_entry = &self.table_entries[index];

4
pci/src/vfio.rs
View file

@ -642,7 +642,7 @@ impl VfioCommon {
PCI_CONFIG_BAR_PREFETCHABLE
) {
prefetchable = PciBarPrefetchable::Prefetchable
};
}
// To get size write all 1s
self.vfio_wrapper
@ -941,7 +941,7 @@ impl VfioCommon {
PciCapabilityId::PciExpress => pci_express_cap_found = true,
PciCapabilityId::PowerManagement => power_management_cap_found = true,
_ => {}
};
}
let cap_next = self.vfio_wrapper.read_config_byte((cap_iter + 1).into())
& PCI_CONFIG_CAPABILITY_PTR_MASK;