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pci: Fix vector control read/write from/to MSI-X table

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The vector control offset is at the 4th byte of each MSI-X table entry.
For that reason, it is located at 0xc, and not 0x10 as implemented.

This commit fixes the current MSI-X code, allowing proper reading and
writing of each vector control register in the MSI-X table.

Fixes #156

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
This commit is contained in:
Sebastien Boeuf 2019-08-07 14:39:43 -07:00 • committed by Rob Bradford
parent fca911e5f3
commit 87195c9ccc
1 changed files with 2 additions and 2 deletions
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4
pci/src/msix.rs
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@ -111,7 +111,7 @@ impl MsixConfig {
0x0 => self.table_entries[index].msg_addr_lo,
0x4 => self.table_entries[index].msg_addr_hi,
0x8 => self.table_entries[index].msg_data,
0x10 => self.table_entries[index].vector_ctl,
0xc => self.table_entries[index].vector_ctl,
_ => {
error!("invalid offset");
0
@ -162,7 +162,7 @@ impl MsixConfig {
0x0 => self.table_entries[index].msg_addr_lo = value,
0x4 => self.table_entries[index].msg_addr_hi = value,
0x8 => self.table_entries[index].msg_data = value,
0x10 => {
0xc => {
old_entry = Some(self.table_entries[index].clone());
self.table_entries[index].vector_ctl = value;
}