From 968902dfec34a693ff908d4f02a15964bf6150a8 Mon Sep 17 00:00:00 2001
From: Rob Bradford <robert.bradford@intel.com>
Date: Fri, 3 Sep 2021 10:27:21 +0100
Subject: [PATCH] devices, vmm: Upgrade exit reasons to info!() level debugging

These statements are useful for understanding the cause of reset or
shutdown of the VM and are not spammy so should be included at info!()
level.

Signed-off-by: Rob Bradford <robert.bradford@intel.com>
---
 devices/src/acpi.rs         | 4 ++--
 devices/src/legacy/i8042.rs | 2 +-
 vmm/src/cpu.rs              | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/devices/src/acpi.rs b/devices/src/acpi.rs
index e11449e2f..b37e7cbea 100644
--- a/devices/src/acpi.rs
+++ b/devices/src/acpi.rs
@@ -41,7 +41,7 @@ impl BusDevice for AcpiShutdownDevice {
 
     fn write(&mut self, _base: u64, _offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
         if data[0] == 1 {
-            debug!("ACPI Reboot signalled");
+            info!("ACPI Reboot signalled");
             if let Err(e) = self.reset_evt.write(1) {
                 error!("Error triggering ACPI reset event: {}", e);
             }
@@ -51,7 +51,7 @@ impl BusDevice for AcpiShutdownDevice {
         const SLEEP_STATUS_EN_BIT: u8 = 5;
         const SLEEP_VALUE_BIT: u8 = 2;
         if data[0] == (S5_SLEEP_VALUE << SLEEP_VALUE_BIT) | (1 << SLEEP_STATUS_EN_BIT) {
-            debug!("ACPI Shutdown signalled");
+            info!("ACPI Shutdown signalled");
             if let Err(e) = self.exit_evt.write(1) {
                 error!("Error triggering ACPI shutdown event: {}", e);
             }
diff --git a/devices/src/legacy/i8042.rs b/devices/src/legacy/i8042.rs
index c38fe735c..5192bbde6 100644
--- a/devices/src/legacy/i8042.rs
+++ b/devices/src/legacy/i8042.rs
@@ -34,7 +34,7 @@ impl BusDevice for I8042Device {
 
     fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
         if data.len() == 1 && data[0] == 0xfe && offset == 3 {
-            debug!("i8042 reset signalled");
+            info!("i8042 reset signalled");
             if let Err(e) = self.reset_evt.write(1) {
                 error!("Error triggering i8042 reset event: {}", e);
             }
diff --git a/vmm/src/cpu.rs b/vmm/src/cpu.rs
index 6161fc6cb..8f5b31dbc 100644
--- a/vmm/src/cpu.rs
+++ b/vmm/src/cpu.rs
@@ -786,13 +786,13 @@ impl CpuManager {
                                     VmExit::Ignore => {}
                                     VmExit::Hyperv => {}
                                     VmExit::Reset => {
-                                        debug!("VmExit::Reset");
+                                        info!("VmExit::Reset");
                                         vcpu_run_interrupted.store(true, Ordering::SeqCst);
                                         reset_evt.write(1).unwrap();
                                         break;
                                     }
                                     VmExit::Shutdown => {
-                                        debug!("VmExit::Shutdown");
+                                        info!("VmExit::Shutdown");
                                         vcpu_run_interrupted.store(true, Ordering::SeqCst);
                                         exit_evt.write(1).unwrap();
                                         break;