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misc: clippy: add semicolon_if_nothing_returned

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Signed-off-by: Philipp Schuster <philipp.schuster@cyberus-technology.de>
On-behalf-of: SAP philipp.schuster@sap.com
This commit is contained in:
Philipp Schuster 2025-11-18 12:26:21 +01:00 • committed by Rob Bradford
parent ea4f07d3bf
commit b4c62bf159
64 changed files with 244 additions and 236 deletions
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14
pci/src/msi.rs
View file

@ -142,8 +142,9 @@ impl MsiCap {
let value = LittleEndian::read_u16(data);
match offset {
MSI_MSG_CTL_OFFSET => {
self.msg_ctl = (self.msg_ctl & !(MSI_CTL_ENABLE | MSI_CTL_MULTI_MSG_ENABLE))
| (value & (MSI_CTL_ENABLE | MSI_CTL_MULTI_MSG_ENABLE))
self.msg_ctl = (self.msg_ctl
& !(MSI_CTL_ENABLE | MSI_CTL_MULTI_MSG_ENABLE))
| (value & (MSI_CTL_ENABLE | MSI_CTL_MULTI_MSG_ENABLE));
}
x if x == msg_data_offset => self.msg_data = value,
_ => error!("invalid offset"),
@ -153,16 +154,17 @@ impl MsiCap {
let value = LittleEndian::read_u32(data);
match offset {
0x0 => {
self.msg_ctl = (self.msg_ctl & !(MSI_CTL_ENABLE | MSI_CTL_MULTI_MSG_ENABLE))
| ((value >> 16) as u16 & (MSI_CTL_ENABLE | MSI_CTL_MULTI_MSG_ENABLE))
self.msg_ctl = (self.msg_ctl
& !(MSI_CTL_ENABLE | MSI_CTL_MULTI_MSG_ENABLE))
| ((value >> 16) as u16 & (MSI_CTL_ENABLE | MSI_CTL_MULTI_MSG_ENABLE));
}
MSI_MSG_ADDR_LO_OFFSET => self.msg_addr_lo = value & MSI_MSG_ADDR_LO_MASK,
x if x == msg_data_offset => self.msg_data = value as u16,
x if addr_hi_offset.is_some() && x == addr_hi_offset.unwrap() => {
self.msg_addr_hi = value
self.msg_addr_hi = value;
}
x if mask_bits_offset.is_some() && x == mask_bits_offset.unwrap() => {
self.mask_bits = value
self.mask_bits = value;
}
_ => error!("invalid offset"),
}

20
pci/src/vfio.rs
View file

@ -238,14 +238,14 @@ impl Interrupt {
fn msix_write_table(&mut self, offset: u64, data: &[u8]) {
if let Some(msix) = &mut self.msix {
let offset = offset - u64::from(msix.cap.table_offset());
msix.bar.write_table(offset, data)
msix.bar.write_table(offset, data);
}
}
fn msix_read_table(&self, offset: u64, data: &mut [u8]) {
if let Some(msix) = &self.msix {
let offset = offset - u64::from(msix.cap.table_offset());
msix.bar.read_table(offset, data)
msix.bar.read_table(offset, data);
}
}
@ -344,7 +344,7 @@ pub(crate) trait Vfio: Send + Sync {
fn write_config_dword(&self, offset: u32, buf: u32) {
let data: [u8; 4] = buf.to_le_bytes();
self.write_config(offset, &data)
self.write_config(offset, &data);
}
fn read_config(&self, offset: u32, data: &mut [u8]) {
@ -352,7 +352,7 @@ pub(crate) trait Vfio: Send + Sync {
}
fn write_config(&self, offset: u32, data: &[u8]) {
self.region_write(VFIO_PCI_CONFIG_REGION_INDEX, offset.into(), data)
self.region_write(VFIO_PCI_CONFIG_REGION_INDEX, offset.into(), data);
}
fn enable_msi(&self, fds: Vec<&EventFd>) -> Result<(), VfioError> {
@ -408,11 +408,11 @@ impl VfioDeviceWrapper {
impl Vfio for VfioDeviceWrapper {
fn region_read(&self, index: u32, offset: u64, data: &mut [u8]) {
self.device.region_read(index, data, offset)
self.device.region_read(index, data, offset);
}
fn region_write(&self, index: u32, offset: u64, data: &[u8]) {
self.device.region_write(index, data, offset)
self.device.region_write(index, data, offset);
}
fn get_irq_info(&self, irq_index: u32) -> Option<VfioIrq> {
@ -641,7 +641,7 @@ impl VfioCommon {
flags & PCI_CONFIG_BAR_PREFETCHABLE,
PCI_CONFIG_BAR_PREFETCHABLE
) {
prefetchable = PciBarPrefetchable::Prefetchable
prefetchable = PciBarPrefetchable::Prefetchable;
}
// To get size write all 1s
@ -1786,7 +1786,7 @@ impl Drop for VfioPciDevice {
if let Some(msi) = &self.common.interrupt.msi
&& msi.cfg.enabled()
{
self.common.disable_msi()
self.common.disable_msi();
}
if self.common.interrupt.intx_in_use() {
@ -1797,7 +1797,7 @@ impl Drop for VfioPciDevice {
impl BusDevice for VfioPciDevice {
fn read(&mut self, base: u64, offset: u64, data: &mut [u8]) {
self.read_bar(base, offset, data)
self.read_bar(base, offset, data);
}
fn write(&mut self, base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
@ -1870,7 +1870,7 @@ impl PciDevice for VfioPciDevice {
}
fn read_bar(&mut self, base: u64, offset: u64, data: &mut [u8]) {
self.common.read_bar(base, offset, data)
self.common.read_bar(base, offset, data);
}
fn write_bar(&mut self, base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {

6
pci/src/vfio_user.rs
View file

@ -274,7 +274,7 @@ impl VfioUserPciDevice {
impl BusDevice for VfioUserPciDevice {
fn read(&mut self, base: u64, offset: u64, data: &mut [u8]) {
self.read_bar(base, offset, data)
self.read_bar(base, offset, data);
}
fn write(&mut self, base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
@ -440,7 +440,7 @@ impl PciDevice for VfioUserPciDevice {
}
fn read_bar(&mut self, base: u64, offset: u64, data: &mut [u8]) {
self.common.read_bar(base, offset, data)
self.common.read_bar(base, offset, data);
}
fn write_bar(&mut self, base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
@ -514,7 +514,7 @@ impl Drop for VfioUserPciDevice {
if let Some(msi) = &self.common.interrupt.msi
&& msi.cfg.enabled()
{
self.common.disable_msi()
self.common.disable_msi();
}
if self.common.interrupt.intx_in_use() {