From bfc65bff2a5bdb9aca7dcd3284a0ced0e5cc7db8 Mon Sep 17 00:00:00 2001 From: Rob Bradford Date: Wed, 21 Apr 2021 15:00:53 +0100 Subject: [PATCH] virtio-devices: transport: Naturally align capability PCI bar The PCI bar should be naturally aligned i.e. aligned to the size of the bar itself. Signed-off-by: Rob Bradford --- virtio-devices/src/transport/pci_device.rs | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/virtio-devices/src/transport/pci_device.rs b/virtio-devices/src/transport/pci_device.rs index bf4a67e02..01ec03300 100644 --- a/virtio-devices/src/transport/pci_device.rs +++ b/virtio-devices/src/transport/pci_device.rs @@ -832,14 +832,22 @@ impl PciDevice for VirtioPciDevice { let (virtio_pci_bar_addr, region_type) = if self.use_64bit_bar { let region_type = PciBarRegionType::Memory64BitRegion; let addr = allocator - .allocate_mmio_addresses(self.settings_bar_addr, CAPABILITY_BAR_SIZE, None) + .allocate_mmio_addresses( + self.settings_bar_addr, + CAPABILITY_BAR_SIZE, + Some(CAPABILITY_BAR_SIZE), + ) .ok_or(PciDeviceError::IoAllocationFailed(CAPABILITY_BAR_SIZE))?; ranges.push((addr, CAPABILITY_BAR_SIZE, region_type)); (addr, region_type) } else { let region_type = PciBarRegionType::Memory32BitRegion; let addr = allocator - .allocate_mmio_hole_addresses(self.settings_bar_addr, CAPABILITY_BAR_SIZE, None) + .allocate_mmio_hole_addresses( + self.settings_bar_addr, + CAPABILITY_BAR_SIZE, + Some(CAPABILITY_BAR_SIZE), + ) .ok_or(PciDeviceError::IoAllocationFailed(CAPABILITY_BAR_SIZE))?; ranges.push((addr, CAPABILITY_BAR_SIZE, region_type)); (addr, region_type)