diff --git a/Cargo.lock b/Cargo.lock index d25780472..1596019d5 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -564,7 +564,7 @@ dependencies = [ [[package]] name = "mshv-bindings" version = "0.1.0" -source = "git+https://github.com/rust-vmm/mshv?branch=main#99da566389546aedb56fc3d279e01c5dbde79bce" +source = "git+https://github.com/rust-vmm/mshv?branch=main#424f51a5fc40f30a7787576981dd549950677420" dependencies = [ "libc", "serde", @@ -576,7 +576,7 @@ dependencies = [ [[package]] name = "mshv-ioctls" version = "0.1.0" -source = "git+https://github.com/rust-vmm/mshv?branch=main#99da566389546aedb56fc3d279e01c5dbde79bce" +source = "git+https://github.com/rust-vmm/mshv?branch=main#424f51a5fc40f30a7787576981dd549950677420" dependencies = [ "libc", "mshv-bindings", diff --git a/hypervisor/src/cpu.rs b/hypervisor/src/cpu.rs index 1cffb88ed..803eaccca 100644 --- a/hypervisor/src/cpu.rs +++ b/hypervisor/src/cpu.rs @@ -174,6 +174,16 @@ pub enum HypervisorCpuError { #[error("Failed to get debug registers: {0}")] GetDebugRegs(#[source] anyhow::Error), /// + /// Setting misc register error + /// + #[error("Failed to set misc registers: {0}")] + SetMiscRegs(#[source] anyhow::Error), + /// + /// Getting misc register error + /// + #[error("Failed to get misc registers: {0}")] + GetMiscRegs(#[source] anyhow::Error), + /// /// Write to Guest Mem /// #[error("Failed to write to Guest Mem at: {0}")] diff --git a/hypervisor/src/mshv/mod.rs b/hypervisor/src/mshv/mod.rs index 5c65af935..071d33d4b 100644 --- a/hypervisor/src/mshv/mod.rs +++ b/hypervisor/src/mshv/mod.rs @@ -506,6 +506,13 @@ impl cpu::Vcpu for MshvVcpu { self.set_xcrs(&state.xcrs)?; self.set_lapic(&state.lapic)?; self.set_xsave(&state.xsave)?; + // These registers are global and needed to be set only for first VCPU + // as Microsoft Hypervisor allows setting this regsier for only one VCPU + if self.vp_index == 0 { + self.fd + .set_misc_regs(&state.misc) + .map_err(|e| cpu::HypervisorCpuError::SetMiscRegs(e.into()))? + } self.fd .set_debug_regs(&state.dbg) .map_err(|e| cpu::HypervisorCpuError::SetDebugRegs(e.into()))?; @@ -524,10 +531,15 @@ impl cpu::Vcpu for MshvVcpu { self.get_msrs(&mut msrs)?; let lapic = self.get_lapic()?; let xsave = self.get_xsave()?; + let misc = self + .fd + .get_misc_regs() + .map_err(|e| cpu::HypervisorCpuError::GetMiscRegs(e.into()))?; let dbg = self .fd .get_debug_regs() .map_err(|e| cpu::HypervisorCpuError::GetDebugRegs(e.into()))?; + Ok(CpuState { msrs, vcpu_events, @@ -538,6 +550,7 @@ impl cpu::Vcpu for MshvVcpu { lapic, dbg, xsave, + misc, }) } #[cfg(target_arch = "x86_64")] diff --git a/hypervisor/src/mshv/x86_64/mod.rs b/hypervisor/src/mshv/x86_64/mod.rs index c8bef165c..0b9e8eded 100644 --- a/hypervisor/src/mshv/x86_64/mod.rs +++ b/hypervisor/src/mshv/x86_64/mod.rs @@ -18,10 +18,11 @@ pub use { mshv_bindings::mshv_user_mem_region as MemoryRegion, mshv_bindings::msr_entry as MsrEntry, mshv_bindings::CpuId, mshv_bindings::DebugRegisters, mshv_bindings::FloatingPointUnit as FpuState, mshv_bindings::LapicState, - mshv_bindings::MsrList, mshv_bindings::Msrs as MsrEntries, mshv_bindings::Msrs, - mshv_bindings::SegmentRegister, mshv_bindings::SpecialRegisters, - mshv_bindings::StandardRegisters, mshv_bindings::SuspendRegisters, mshv_bindings::VcpuEvents, - mshv_bindings::XSave as Xsave, mshv_bindings::Xcrs as ExtendedControlRegisters, + mshv_bindings::MiscRegs as MiscRegisters, mshv_bindings::MsrList, + mshv_bindings::Msrs as MsrEntries, mshv_bindings::Msrs, mshv_bindings::SegmentRegister, + mshv_bindings::SpecialRegisters, mshv_bindings::StandardRegisters, + mshv_bindings::SuspendRegisters, mshv_bindings::VcpuEvents, mshv_bindings::XSave as Xsave, + mshv_bindings::Xcrs as ExtendedControlRegisters, }; #[derive(Clone, Serialize, Deserialize)] @@ -35,6 +36,7 @@ pub struct VcpuMshvState { pub lapic: LapicState, pub dbg: DebugRegisters, pub xsave: Xsave, + pub misc: MiscRegisters, } impl fmt::Display for VcpuMshvState {