hypervisor: Refactor common PSTATE register definition
Initial PSTATE value would be same for both KVM and MSHV. Thus, move it to common register definition pool. Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
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2 changed files with 14 additions and 13 deletions
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@ -164,3 +164,14 @@ pub enum ExceptionClass {
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VECTOR_CATCH_32 = 0b111010,
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BRK = 0b111100,
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}
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#[allow(non_upper_case_globals)]
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// PSR (Processor State Register) bits.
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// Taken from arch/arm64/include/uapi/asm/ptrace.h.
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const PSR_MODE_EL1h: u64 = 0x0000_0005;
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const PSR_F_BIT: u64 = 0x0000_0040;
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const PSR_I_BIT: u64 = 0x0000_0080;
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const PSR_A_BIT: u64 = 0x0000_0100;
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const PSR_D_BIT: u64 = 0x0000_0200;
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// Taken from arch/arm64/kvm/inject_fault.c.
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pub const PSTATE_FAULT_BITS_64: u64 = PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | PSR_I_BIT | PSR_D_BIT;
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@ -77,6 +77,8 @@ pub mod aarch64;
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#[cfg(target_arch = "riscv64")]
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pub mod riscv64;
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#[cfg(target_arch = "aarch64")]
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use crate::arch::aarch64::regs;
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#[cfg(target_arch = "aarch64")]
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use std::mem;
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///
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@ -2289,18 +2291,6 @@ impl cpu::Vcpu for KvmVcpu {
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///
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#[cfg(target_arch = "aarch64")]
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fn setup_regs(&self, cpu_id: u8, boot_ip: u64, fdt_start: u64) -> cpu::Result<()> {
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#[allow(non_upper_case_globals)]
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// PSR (Processor State Register) bits.
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// Taken from arch/arm64/include/uapi/asm/ptrace.h.
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const PSR_MODE_EL1h: u64 = 0x0000_0005;
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const PSR_F_BIT: u64 = 0x0000_0040;
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const PSR_I_BIT: u64 = 0x0000_0080;
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const PSR_A_BIT: u64 = 0x0000_0100;
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const PSR_D_BIT: u64 = 0x0000_0200;
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// Taken from arch/arm64/kvm/inject_fault.c.
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const PSTATE_FAULT_BITS_64: u64 =
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PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | PSR_I_BIT | PSR_D_BIT;
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let kreg_off = offset_of!(kvm_regs, regs);
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// Get the register index of the PSTATE (Processor State) register.
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@ -2310,7 +2300,7 @@ impl cpu::Vcpu for KvmVcpu {
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.unwrap()
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.set_one_reg(
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arm64_core_reg_id!(KVM_REG_SIZE_U64, pstate),
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&PSTATE_FAULT_BITS_64.to_le_bytes(),
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®s::PSTATE_FAULT_BITS_64.to_le_bytes(),
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)
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.map_err(|e| cpu::HypervisorCpuError::SetAarchCoreRegister(e.into()))?;
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