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misc: clippy: add uninlined_format_args

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Signed-off-by: Philipp Schuster <philipp.schuster@cyberus-technology.de>
On-behalf-of: SAP philipp.schuster@sap.com
This commit is contained in:
Philipp Schuster 2025-11-18 12:24:47 +01:00 • committed by Rob Bradford
parent 7cb73e9e56
commit ea4f07d3bf
23 changed files with 91 additions and 130 deletions
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16
hypervisor/src/arch/x86/emulator/instructions/mod.rs
View file

@ -25,15 +25,13 @@ fn get_op<T: CpuStateManager>(
) -> Result<u64, PlatformError> {
if insn.op_count() < op_index + 1 {
return Err(PlatformError::InvalidOperand(anyhow!(
"Invalid operand {:?}",
op_index
"Invalid operand {op_index:?}"
)));
}
if !matches!(op_size, 1 | 2 | 4 | 8) {
return Err(PlatformError::InvalidOperand(anyhow!(
"Invalid operand size {:?}",
op_size
"Invalid operand size {op_size:?}"
)));
}
@ -59,7 +57,7 @@ fn get_op<T: CpuStateManager>(
OpKind::Immediate32 => insn.immediate32() as u64,
OpKind::Immediate32to64 => insn.immediate32to64() as u64,
OpKind::Immediate64 => insn.immediate64(),
k => return Err(PlatformError::InvalidOperand(anyhow!("{:?}", k))),
k => return Err(PlatformError::InvalidOperand(anyhow!("{k:?}"))),
};
Ok(value)
@ -75,15 +73,13 @@ fn set_op<T: CpuStateManager>(
) -> Result<(), PlatformError> {
if insn.op_count() < op_index + 1 {
return Err(PlatformError::InvalidOperand(anyhow!(
"Invalid operand {:?}",
op_index
"Invalid operand {op_index:?}"
)));
}
if !matches!(op_size, 1 | 2 | 4 | 8) {
return Err(PlatformError::InvalidOperand(anyhow!(
"Invalid operand size {:?}",
op_size
"Invalid operand size {op_size:?}"
)));
}
@ -100,7 +96,7 @@ fn set_op<T: CpuStateManager>(
let addr = memory_operand_address(insn, state, true)?;
platform.write_memory(addr, &value.to_le_bytes()[..op_size])?;
}
k => return Err(PlatformError::InvalidOperand(anyhow!("{:?}", k))),
k => return Err(PlatformError::InvalidOperand(anyhow!("{k:?}"))),
}
Ok(())

42
hypervisor/src/arch/x86/emulator/mod.rs
View file

@ -136,9 +136,7 @@ pub trait CpuStateManager: Clone {
.checked_add(segment_register.base)
.ok_or_else(|| {
PlatformError::InvalidAddress(anyhow!(
"Logical address {:#x} cannot be linearized with segment {:#x?}",
logical_addr,
segment_register
"Logical address {logical_addr:#x} cannot be linearized with segment {segment_register:#x?}"
))
})?)
}
@ -164,9 +162,7 @@ pub trait CpuStateManager: Clone {
if segment_type_expand_down(segment_type) {
if logical_addr >= segment_limit.into() {
return Err(PlatformError::InvalidAddress(anyhow!(
"{:#x} is off limits {:#x} (expand down)",
logical_addr,
segment_limit
"{logical_addr:#x} is off limits {segment_limit:#x} (expand down)"
)));
}
@ -179,16 +175,14 @@ pub trait CpuStateManager: Clone {
if logical_addr > segment_limit.into() {
return Err(PlatformError::InvalidAddress(anyhow!(
"{:#x} is off limits {:#x}",
logical_addr,
segment_limit
"{logical_addr:#x} is off limits {segment_limit:#x}"
)));
}
Ok(logical_addr.wrapping_add(segment_register.base))
}
_ => Err(PlatformError::UnsupportedCpuMode(anyhow!("{:?}", mode))),
_ => Err(PlatformError::UnsupportedCpuMode(anyhow!("{mode:?}"))),
}
}
}
@ -252,8 +246,7 @@ impl CpuStateManager for EmulatorCpuState {
r => {
return Err(PlatformError::InvalidRegister(anyhow!(
"read_reg invalid GPR {:?}",
r
"read_reg invalid GPR {r:?}"
)));
}
};
@ -276,18 +269,17 @@ impl CpuStateManager for EmulatorCpuState {
}
} else {
return Err(PlatformError::InvalidRegister(anyhow!(
"read_reg invalid GPR {:?}",
reg
"read_reg invalid GPR {reg:?}"
)));
};
debug!("Register read: {:#x} from {:?}", reg_value, reg);
debug!("Register read: {reg_value:#x} from {reg:?}");
Ok(reg_value)
}
fn write_reg(&mut self, reg: Register, val: u64) -> Result<(), PlatformError> {
debug!("Register write: {:#x} to {:?}", val, reg);
debug!("Register write: {val:#x} to {reg:?}");
// SDM Vol 1 - 3.4.1.1
//
@ -312,8 +304,7 @@ impl CpuStateManager for EmulatorCpuState {
}
} else {
return Err(PlatformError::InvalidRegister(anyhow!(
"write_reg invalid register {:?}",
reg
"write_reg invalid register {reg:?}"
)));
};
@ -373,8 +364,7 @@ impl CpuStateManager for EmulatorCpuState {
Register::CR8 => set_reg!(self.sregs.cr8, mask, reg_value),
_ => {
return Err(PlatformError::InvalidRegister(anyhow!(
"write_reg invalid register {:?}",
reg
"write_reg invalid register {reg:?}"
)));
}
}
@ -385,8 +375,7 @@ impl CpuStateManager for EmulatorCpuState {
fn read_segment(&self, reg: Register) -> Result<SegmentRegister, PlatformError> {
if !reg.is_segment_register() {
return Err(PlatformError::InvalidRegister(anyhow!(
"read_segment {:?} is not a segment register",
reg
"read_segment {reg:?} is not a segment register"
)));
}
@ -398,8 +387,7 @@ impl CpuStateManager for EmulatorCpuState {
Register::GS => Ok(self.sregs.gs),
Register::SS => Ok(self.sregs.ss),
r => Err(PlatformError::InvalidRegister(anyhow!(
"read_segment invalid register {:?}",
r
"read_segment invalid register {r:?}"
))),
}
}
@ -410,7 +398,7 @@ impl CpuStateManager for EmulatorCpuState {
segment_register: SegmentRegister,
) -> Result<(), PlatformError> {
if !reg.is_segment_register() {
return Err(PlatformError::InvalidRegister(anyhow!("{:?}", reg)));
return Err(PlatformError::InvalidRegister(anyhow!("{reg:?}")));
}
match reg {
@ -420,7 +408,7 @@ impl CpuStateManager for EmulatorCpuState {
Register::FS => self.sregs.fs = segment_register,
Register::GS => self.sregs.gs = segment_register,
Register::SS => self.sregs.ss = segment_register,
r => return Err(PlatformError::InvalidRegister(anyhow!("{:?}", r))),
r => return Err(PlatformError::InvalidRegister(anyhow!("{r:?}"))),
}
Ok(())
@ -590,7 +578,7 @@ impl<T: CpuStateManager> Emulator<'_, T> {
.fetch(last_decoded_ip, &mut fetched_insn_stream)
.map_err(EmulationError::PlatformEmulationError)?;
debug!("Fetched {:x?}", fetched_insn_stream);
debug!("Fetched {fetched_insn_stream:x?}");
// Once we have the new stream, we must create a new decoder
// and emulate one last instruction from the last decoded IP.

6
hypervisor/src/kvm/mod.rs
View file

@ -627,7 +627,7 @@ impl vm::Vm for KvmVm {
///
fn create_vgic(&self, config: VgicConfig) -> vm::Result<Arc<Mutex<dyn Vgic>>> {
let gic_device = KvmGicV3Its::new(self, config)
.map_err(|e| vm::HypervisorVmError::CreateVgic(anyhow!("Vgic error {:?}", e)))?;
.map_err(|e| vm::HypervisorVmError::CreateVgic(anyhow!("Vgic error {e:?}")))?;
Ok(Arc::new(Mutex::new(gic_device)))
}
@ -1971,9 +1971,7 @@ impl cpu::Vcpu for KvmVcpu {
Ok(cpu::VmExit::Shutdown)
} else {
Err(cpu::HypervisorCpuError::RunVcpu(anyhow!(
"Unexpected system event with type 0x{:x}, flags 0x{:x?}",
event_type,
flags
"Unexpected system event with type 0x{event_type:x}, flags 0x{flags:x?}",
)))
}
}

56
hypervisor/src/mshv/mod.rs
View file

@ -705,7 +705,7 @@ impl cpu::Vcpu for MshvVcpu {
let gva = info.guest_virtual_address;
let gpa = info.guest_physical_address;
debug!("Unmapped GPA exit: GVA {:x} GPA {:x}", gva, gpa);
debug!("Unmapped GPA exit: GVA {gva:x} GPA {gpa:x}");
let context = MshvEmulatorContext {
vcpu: self,
@ -739,7 +739,7 @@ impl cpu::Vcpu for MshvVcpu {
let gva = info.guest_virtual_address;
let gpa = info.guest_physical_address;
debug!("Exit ({:?}) GVA {:x} GPA {:x}", msg_type, gva, gpa);
debug!("Exit ({msg_type:?}) GVA {gva:x} GPA {gpa:x}");
let mut context = MshvEmulatorContext {
vcpu: self,
@ -777,8 +777,7 @@ impl cpu::Vcpu for MshvVcpu {
assert!(num_ranges >= 1);
if num_ranges > 1 {
return Err(cpu::HypervisorCpuError::RunVcpu(anyhow!(
"Unhandled VCPU exit(GPA_ATTRIBUTE_INTERCEPT): Expected num_ranges to be 1 but found num_ranges {:?}",
num_ranges
"Unhandled VCPU exit(GPA_ATTRIBUTE_INTERCEPT): Expected num_ranges to be 1 but found num_ranges {num_ranges:?}"
)));
}
@ -786,10 +785,7 @@ impl cpu::Vcpu for MshvVcpu {
let mut gpas = Vec::new();
let ranges = info.ranges;
let (gfn_start, gfn_count) = snp::parse_gpa_range(ranges[0]).unwrap();
debug!(
"Releasing pages: gfn_start: {:x?}, gfn_count: {:?}",
gfn_start, gfn_count
);
debug!("Releasing pages: gfn_start: {gfn_start:x?}, gfn_count: {gfn_count:?}");
let gpa_start = gfn_start * HV_PAGE_SIZE as u64;
for i in 0..gfn_count {
gpas.push(gpa_start + i * HV_PAGE_SIZE as u64);
@ -818,7 +814,7 @@ impl cpu::Vcpu for MshvVcpu {
self.vm_fd
.modify_gpa_host_access(&gpa_list[0])
.map_err(|e| cpu::HypervisorCpuError::RunVcpu(anyhow!(
"Unhandled VCPU exit: attribute intercept - couldn't modify host access {}", e
"Unhandled VCPU exit: attribute intercept - couldn't modify host access {e}"
)))?;
// Guest is revoking the shared access, so we need to update the bitmap
self.host_access_pages.rcu(|_bitmap| {
@ -835,9 +831,7 @@ impl cpu::Vcpu for MshvVcpu {
let gpa = info.guest_physical_address;
Err(cpu::HypervisorCpuError::RunVcpu(anyhow!(
"Unhandled VCPU exit: Unaccepted GPA({:x}) found at GVA({:x})",
gpa,
gva,
"Unhandled VCPU exit: Unaccepted GPA({gpa:x}) found at GVA({gva:x})",
)))
}
#[cfg(target_arch = "x86_64")]
@ -905,8 +899,7 @@ impl cpu::Vcpu for MshvVcpu {
<< GHCB_INFO_BIT_WIDTH)
as u64;
debug!(
"GHCB_INFO_HYP_FEATURE_REQUEST: Supported features: {:0x}",
ghcb_response
"GHCB_INFO_HYP_FEATURE_REQUEST: Supported features: {ghcb_response:0x}"
);
let arr_reg_name_value =
[(hv_register_name_HV_X64_REGISTER_GHCB, ghcb_response)];
@ -1182,8 +1175,7 @@ impl cpu::Vcpu for MshvVcpu {
.map_err(|e| cpu::HypervisorCpuError::RunVcpu(e.into()))?;
debug!(
"SNP guest request: req_gpa {:0x} rsp_gpa {:0x}",
req_gpa, rsp_gpa
"SNP guest request: req_gpa {req_gpa:0x} rsp_gpa {rsp_gpa:0x}"
);
set_svm_field_u64_ptr!(ghcb, exit_info2, 0);
@ -1194,8 +1186,7 @@ impl cpu::Vcpu for MshvVcpu {
let apic_id =
info.__bindgen_anon_2.__bindgen_anon_1.sw_exit_info1 >> 32;
debug!(
"SNP AP CREATE REQUEST with VMSA GPA {:0x}, and APIC ID {:?}",
vmsa_gpa, apic_id
"SNP AP CREATE REQUEST with VMSA GPA {vmsa_gpa:0x}, and APIC ID {apic_id:?}"
);
let mshv_ap_create_req = mshv_sev_snp_ap_create {
@ -1220,16 +1211,14 @@ impl cpu::Vcpu for MshvVcpu {
Ok(cpu::VmExit::Ignore)
}
exit => Err(cpu::HypervisorCpuError::RunVcpu(anyhow!(
"Unhandled VCPU exit {:?}",
exit
"Unhandled VCPU exit {exit:?}"
))),
},
Err(e) => match e.errno() {
libc::EAGAIN | libc::EINTR => Ok(cpu::VmExit::Ignore),
_ => Err(cpu::HypervisorCpuError::RunVcpu(anyhow!(
"VCPU error {:?}",
e
"VCPU error {e:?}"
))),
},
}
@ -1576,7 +1565,7 @@ impl MshvVcpu {
// SAFETY: Accessing a union element from bindgen generated bindings.
let prev_ghcb_gpa = unsafe { reg_assocs[0].value.reg64 };
debug!("Prev GHCB GPA is {:x}", prev_ghcb_gpa);
debug!("Prev GHCB GPA is {prev_ghcb_gpa:x}");
let mut ghcb_gpa = hv_x64_register_sev_ghcb::default();
@ -2224,7 +2213,7 @@ impl vm::Vm for MshvVm {
#[cfg(target_arch = "aarch64")]
fn create_vgic(&self, config: VgicConfig) -> vm::Result<Arc<Mutex<dyn Vgic>>> {
let gic_device = MshvGicV2M::new(self, config)
.map_err(|e| vm::HypervisorVmError::CreateVgic(anyhow!("Vgic error {:?}", e)))?;
.map_err(|e| vm::HypervisorVmError::CreateVgic(anyhow!("Vgic error {e:?}")))?;
// Register GICD address with the hypervisor
self.fd
@ -2233,7 +2222,7 @@ impl vm::Vm for MshvVm {
gic_device.dist_addr,
)
.map_err(|e| {
vm::HypervisorVmError::CreateVgic(anyhow!("Failed to set GICD address: {}", e))
vm::HypervisorVmError::CreateVgic(anyhow!("Failed to set GICD address: {e}"))
})?;
// Register GITS address with the hypervisor
@ -2244,7 +2233,7 @@ impl vm::Vm for MshvVm {
gic_device.gits_addr,
)
.map_err(|e| {
vm::HypervisorVmError::CreateVgic(anyhow!("Failed to set GITS address: {}", e))
vm::HypervisorVmError::CreateVgic(anyhow!("Failed to set GITS address: {e}"))
})?;
Ok(Arc::new(Mutex::new(gic_device)))
@ -2265,8 +2254,7 @@ impl vm::Vm for MshvVm {
)
.map_err(|e| {
vm::HypervisorVmError::SetVmProperty(anyhow!(
"Failed to set partition property: {}",
e
"Failed to set partition property: {e}"
))
})
}
@ -2281,8 +2269,7 @@ impl vm::Vm for MshvVm {
)
.map_err(|e| {
vm::HypervisorVmError::SetVmProperty(anyhow!(
"Failed to set partition property: {}",
e
"Failed to set partition property: {e}"
))
})
}
@ -2363,8 +2350,7 @@ impl vm::Vm for MshvVm {
)
.map_err(|e| {
vm::HypervisorVmError::InitializeVm(anyhow!(
"Failed to set GIC LPI support: {}",
e
"Failed to set GIC LPI support: {e}",
))
})?;
@ -2375,8 +2361,7 @@ impl vm::Vm for MshvVm {
)
.map_err(|e| {
vm::HypervisorVmError::InitializeVm(anyhow!(
"Failed to set arch timer interrupt ID: {}",
e
"Failed to set arch timer interrupt ID: {e}",
))
})?;
@ -2387,8 +2372,7 @@ impl vm::Vm for MshvVm {
)
.map_err(|e| {
vm::HypervisorVmError::InitializeVm(anyhow!(
"Failed to set PMU interrupt ID: {}",
e
"Failed to set PMU interrupt ID: {e}",
))
})?;
}

2
hypervisor/src/mshv/x86_64/emulator.rs
View file

@ -158,7 +158,7 @@ impl PlatformEmulator for MshvEmulatorContext<'_> {
.map_err(|e| PlatformError::GetCpuStateFailure(e.into()))?;
debug!("mshv emulator: Getting new CPU state");
debug!("mshv emulator: {:#x?}", regs);
debug!("mshv emulator: {regs:#x?}");
Ok(EmulatorCpuState { regs, sregs })
}