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misc: clippy: add uninlined_format_args

Browse source 
Signed-off-by: Philipp Schuster <philipp.schuster@cyberus-technology.de>
On-behalf-of: SAP philipp.schuster@sap.com
This commit is contained in:
Philipp Schuster 2025-11-18 12:24:47 +01:00 • committed by Rob Bradford
parent 7cb73e9e56
commit ea4f07d3bf
23 changed files with 91 additions and 130 deletions
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1
Cargo.toml
View file

@ -172,6 +172,7 @@ suspicious = "deny"
# Individual Lints
assertions_on_result_states = "deny"
undocumented_unsafe_blocks = "deny"
uninlined_format_args = "deny"
unnecessary_semicolon = "deny"
[workspace.lints.rust]

2
arch/src/x86_64/mod.rs
View file

@ -622,7 +622,7 @@ pub fn generate_common_cpuid(
let caps = hypervisor
.tdx_capabilities()
.map_err(Error::TdxCapabilities)?;
info!("TDX capabilities {:#?}", caps);
info!("TDX capabilities {caps:#?}");
Some(caps)
} else {
None

10
block/src/lib.rs
View file

@ -645,7 +645,7 @@ pub fn block_io_uring_is_supported() -> bool {
let io_uring = match IoUring::new(1) {
Ok(io_uring) => io_uring,
Err(e) => {
info!("{} failed to create io_uring instance: {}", error_msg, e);
info!("{error_msg} failed to create io_uring instance: {e}");
return false;
}
};
@ -658,26 +658,26 @@ pub fn block_io_uring_is_supported() -> bool {
match submitter.register_probe(&mut probe) {
Ok(_) => {}
Err(e) => {
info!("{} failed to register a probe: {}", error_msg, e);
info!("{error_msg} failed to register a probe: {e}");
return false;
}
}
// Check IORING_OP_FSYNC is supported
if !probe.is_supported(opcode::Fsync::CODE) {
info!("{} IORING_OP_FSYNC operation not supported", error_msg);
info!("{error_msg} IORING_OP_FSYNC operation not supported");
return false;
}
// Check IORING_OP_READV is supported
if !probe.is_supported(opcode::Readv::CODE) {
info!("{} IORING_OP_READV operation not supported", error_msg);
info!("{error_msg} IORING_OP_READV operation not supported");
return false;
}
// Check IORING_OP_WRITEV is supported
if !probe.is_supported(opcode::Writev::CODE) {
info!("{} IORING_OP_WRITEV operation not supported", error_msg);
info!("{error_msg} IORING_OP_WRITEV operation not supported");
return false;
}

5
devices/src/gic.rs
View file

@ -167,10 +167,7 @@ impl Pausable for Gic {
// Flush tables to guest RAM
let vgic = self.vgic.as_ref().unwrap().clone();
vgic.lock().unwrap().save_data_tables().map_err(|e| {
MigratableError::Pause(anyhow!(
"Could not save GICv3ITS GIC pending tables {:?}",
e
))
MigratableError::Pause(anyhow!("Could not save GICv3ITS GIC pending tables {e:?}",))
})?;
Ok(())
}

2
devices/src/legacy/gpio_pl061.rs
View file

@ -294,7 +294,7 @@ impl BusDevice for Gpio {
if data.len() <= 4 {
let value = read_le_u32(data);
if let Err(e) = self.handle_write(offset, value) {
warn!("Failed to write to GPIO PL061 device: {}", e);
warn!("Failed to write to GPIO PL061 device: {e}");
}
} else {
warn!(

5
devices/src/legacy/rtc_pl031.rs
View file

@ -201,12 +201,11 @@ impl BusDevice for Rtc {
if data.len() <= 4 {
let v = read_le_u32(data);
if let Err(e) = self.handle_write(offset, v) {
warn!("Failed to write to RTC PL031 device: {}", e);
warn!("Failed to write to RTC PL031 device: {e}");
}
} else {
warn!(
"Invalid RTC PL031 write: offset {}, data length {}",
offset,
"Invalid RTC PL031 write: offset {offset}, data length {}",
data.len()
);
}

7
devices/src/legacy/uart_pl011.rs
View file

@ -322,7 +322,7 @@ impl Pl011 {
self.handle_debug();
}
off => {
debug!("PL011: Bad write offset, offset: {}", off);
debug!("PL011: Bad write offset, offset: {off}");
return Err(Error::BadWriteOffset(off));
}
}
@ -424,12 +424,11 @@ impl BusDevice for Pl011 {
if data.len() <= 4 {
let v = read_le_u32(data);
if let Err(e) = self.handle_write(offset, v) {
warn!("Failed to write to PL011 device: {}", e);
warn!("Failed to write to PL011 device: {e}");
}
} else {
warn!(
"Invalid PL011 write: offset {}, data length {}",
offset,
"Invalid PL011 write: offset {offset}, data length {}",
data.len()
);
}

6
devices/src/pvmemcontrol.rs
View file

@ -491,7 +491,7 @@ impl PvmemcontrolBusDevice {
} else {
std::ptr::null()
};
debug!("addr {:X} length {} name {:?}", addr, length, name);
debug!("addr {addr:X} length {length} name {name:?}");
// SAFETY: [`base`, `base` + `len`) is guest memory
self.operate_on_memory_range(addr, length, |base, len| unsafe {
@ -581,7 +581,7 @@ impl PvmemcontrolBusDevice {
..Default::default()
},
Error::GuestMemory(err) => {
warn!("{}", err);
warn!("{err}");
PvmemcontrolResp {
ret_errno: (libc::EINVAL as u32).into(),
ret_code: (func_code as u32).into(),
@ -606,7 +606,7 @@ impl PvmemcontrolBusDevice {
let response: PvmemcontrolResp = match self.handle_request(request) {
Ok(x) => x,
Err(e) => {
warn!("cannot process request {:?} with error {}", request, e);
warn!("cannot process request {request:?} with error {e}");
return;
}
};

16
hypervisor/src/arch/x86/emulator/instructions/mod.rs
View file

@ -25,15 +25,13 @@ fn get_op<T: CpuStateManager>(
) -> Result<u64, PlatformError> {
if insn.op_count() < op_index + 1 {
return Err(PlatformError::InvalidOperand(anyhow!(
"Invalid operand {:?}",
op_index
"Invalid operand {op_index:?}"
)));
}
if !matches!(op_size, 1 | 2 | 4 | 8) {
return Err(PlatformError::InvalidOperand(anyhow!(
"Invalid operand size {:?}",
op_size
"Invalid operand size {op_size:?}"
)));
}
@ -59,7 +57,7 @@ fn get_op<T: CpuStateManager>(
OpKind::Immediate32 => insn.immediate32() as u64,
OpKind::Immediate32to64 => insn.immediate32to64() as u64,
OpKind::Immediate64 => insn.immediate64(),
k => return Err(PlatformError::InvalidOperand(anyhow!("{:?}", k))),
k => return Err(PlatformError::InvalidOperand(anyhow!("{k:?}"))),
};
Ok(value)
@ -75,15 +73,13 @@ fn set_op<T: CpuStateManager>(
) -> Result<(), PlatformError> {
if insn.op_count() < op_index + 1 {
return Err(PlatformError::InvalidOperand(anyhow!(
"Invalid operand {:?}",
op_index
"Invalid operand {op_index:?}"
)));
}
if !matches!(op_size, 1 | 2 | 4 | 8) {
return Err(PlatformError::InvalidOperand(anyhow!(
"Invalid operand size {:?}",
op_size
"Invalid operand size {op_size:?}"
)));
}
@ -100,7 +96,7 @@ fn set_op<T: CpuStateManager>(
let addr = memory_operand_address(insn, state, true)?;
platform.write_memory(addr, &value.to_le_bytes()[..op_size])?;
}
k => return Err(PlatformError::InvalidOperand(anyhow!("{:?}", k))),
k => return Err(PlatformError::InvalidOperand(anyhow!("{k:?}"))),
}
Ok(())

42
hypervisor/src/arch/x86/emulator/mod.rs
View file

@ -136,9 +136,7 @@ pub trait CpuStateManager: Clone {
.checked_add(segment_register.base)
.ok_or_else(|| {
PlatformError::InvalidAddress(anyhow!(
"Logical address {:#x} cannot be linearized with segment {:#x?}",
logical_addr,
segment_register
"Logical address {logical_addr:#x} cannot be linearized with segment {segment_register:#x?}"
))
})?)
}
@ -164,9 +162,7 @@ pub trait CpuStateManager: Clone {
if segment_type_expand_down(segment_type) {
if logical_addr >= segment_limit.into() {
return Err(PlatformError::InvalidAddress(anyhow!(
"{:#x} is off limits {:#x} (expand down)",
logical_addr,
segment_limit
"{logical_addr:#x} is off limits {segment_limit:#x} (expand down)"
)));
}
@ -179,16 +175,14 @@ pub trait CpuStateManager: Clone {
if logical_addr > segment_limit.into() {
return Err(PlatformError::InvalidAddress(anyhow!(
"{:#x} is off limits {:#x}",
logical_addr,
segment_limit
"{logical_addr:#x} is off limits {segment_limit:#x}"
)));
}
Ok(logical_addr.wrapping_add(segment_register.base))
}
_ => Err(PlatformError::UnsupportedCpuMode(anyhow!("{:?}", mode))),
_ => Err(PlatformError::UnsupportedCpuMode(anyhow!("{mode:?}"))),
}
}
}
@ -252,8 +246,7 @@ impl CpuStateManager for EmulatorCpuState {
r => {
return Err(PlatformError::InvalidRegister(anyhow!(
"read_reg invalid GPR {:?}",
r
"read_reg invalid GPR {r:?}"
)));
}
};
@ -276,18 +269,17 @@ impl CpuStateManager for EmulatorCpuState {
}
} else {
return Err(PlatformError::InvalidRegister(anyhow!(
"read_reg invalid GPR {:?}",
reg
"read_reg invalid GPR {reg:?}"
)));
};
debug!("Register read: {:#x} from {:?}", reg_value, reg);
debug!("Register read: {reg_value:#x} from {reg:?}");
Ok(reg_value)
}
fn write_reg(&mut self, reg: Register, val: u64) -> Result<(), PlatformError> {
debug!("Register write: {:#x} to {:?}", val, reg);
debug!("Register write: {val:#x} to {reg:?}");
// SDM Vol 1 - 3.4.1.1
//
@ -312,8 +304,7 @@ impl CpuStateManager for EmulatorCpuState {
}
} else {
return Err(PlatformError::InvalidRegister(anyhow!(
"write_reg invalid register {:?}",
reg
"write_reg invalid register {reg:?}"
)));
};
@ -373,8 +364,7 @@ impl CpuStateManager for EmulatorCpuState {
Register::CR8 => set_reg!(self.sregs.cr8, mask, reg_value),
_ => {
return Err(PlatformError::InvalidRegister(anyhow!(
"write_reg invalid register {:?}",
reg
"write_reg invalid register {reg:?}"
)));
}
}
@ -385,8 +375,7 @@ impl CpuStateManager for EmulatorCpuState {
fn read_segment(&self, reg: Register) -> Result<SegmentRegister, PlatformError> {
if !reg.is_segment_register() {
return Err(PlatformError::InvalidRegister(anyhow!(
"read_segment {:?} is not a segment register",
reg
"read_segment {reg:?} is not a segment register"
)));
}
@ -398,8 +387,7 @@ impl CpuStateManager for EmulatorCpuState {
Register::GS => Ok(self.sregs.gs),
Register::SS => Ok(self.sregs.ss),
r => Err(PlatformError::InvalidRegister(anyhow!(
"read_segment invalid register {:?}",
r
"read_segment invalid register {r:?}"
))),
}
}
@ -410,7 +398,7 @@ impl CpuStateManager for EmulatorCpuState {
segment_register: SegmentRegister,
) -> Result<(), PlatformError> {
if !reg.is_segment_register() {
return Err(PlatformError::InvalidRegister(anyhow!("{:?}", reg)));
return Err(PlatformError::InvalidRegister(anyhow!("{reg:?}")));
}
match reg {
@ -420,7 +408,7 @@ impl CpuStateManager for EmulatorCpuState {
Register::FS => self.sregs.fs = segment_register,
Register::GS => self.sregs.gs = segment_register,
Register::SS => self.sregs.ss = segment_register,
r => return Err(PlatformError::InvalidRegister(anyhow!("{:?}", r))),
r => return Err(PlatformError::InvalidRegister(anyhow!("{r:?}"))),
}
Ok(())
@ -590,7 +578,7 @@ impl<T: CpuStateManager> Emulator<'_, T> {
.fetch(last_decoded_ip, &mut fetched_insn_stream)
.map_err(EmulationError::PlatformEmulationError)?;
debug!("Fetched {:x?}", fetched_insn_stream);
debug!("Fetched {fetched_insn_stream:x?}");
// Once we have the new stream, we must create a new decoder
// and emulate one last instruction from the last decoded IP.

6
hypervisor/src/kvm/mod.rs
View file

@ -627,7 +627,7 @@ impl vm::Vm for KvmVm {
///
fn create_vgic(&self, config: VgicConfig) -> vm::Result<Arc<Mutex<dyn Vgic>>> {
let gic_device = KvmGicV3Its::new(self, config)
.map_err(|e| vm::HypervisorVmError::CreateVgic(anyhow!("Vgic error {:?}", e)))?;
.map_err(|e| vm::HypervisorVmError::CreateVgic(anyhow!("Vgic error {e:?}")))?;
Ok(Arc::new(Mutex::new(gic_device)))
}
@ -1971,9 +1971,7 @@ impl cpu::Vcpu for KvmVcpu {
Ok(cpu::VmExit::Shutdown)
} else {
Err(cpu::HypervisorCpuError::RunVcpu(anyhow!(
"Unexpected system event with type 0x{:x}, flags 0x{:x?}",
event_type,
flags
"Unexpected system event with type 0x{event_type:x}, flags 0x{flags:x?}",
)))
}
}

56
hypervisor/src/mshv/mod.rs
View file

@ -705,7 +705,7 @@ impl cpu::Vcpu for MshvVcpu {
let gva = info.guest_virtual_address;
let gpa = info.guest_physical_address;
debug!("Unmapped GPA exit: GVA {:x} GPA {:x}", gva, gpa);
debug!("Unmapped GPA exit: GVA {gva:x} GPA {gpa:x}");
let context = MshvEmulatorContext {
vcpu: self,
@ -739,7 +739,7 @@ impl cpu::Vcpu for MshvVcpu {
let gva = info.guest_virtual_address;
let gpa = info.guest_physical_address;
debug!("Exit ({:?}) GVA {:x} GPA {:x}", msg_type, gva, gpa);
debug!("Exit ({msg_type:?}) GVA {gva:x} GPA {gpa:x}");
let mut context = MshvEmulatorContext {
vcpu: self,
@ -777,8 +777,7 @@ impl cpu::Vcpu for MshvVcpu {
assert!(num_ranges >= 1);
if num_ranges > 1 {
return Err(cpu::HypervisorCpuError::RunVcpu(anyhow!(
"Unhandled VCPU exit(GPA_ATTRIBUTE_INTERCEPT): Expected num_ranges to be 1 but found num_ranges {:?}",
num_ranges
"Unhandled VCPU exit(GPA_ATTRIBUTE_INTERCEPT): Expected num_ranges to be 1 but found num_ranges {num_ranges:?}"
)));
}
@ -786,10 +785,7 @@ impl cpu::Vcpu for MshvVcpu {
let mut gpas = Vec::new();
let ranges = info.ranges;
let (gfn_start, gfn_count) = snp::parse_gpa_range(ranges[0]).unwrap();
debug!(
"Releasing pages: gfn_start: {:x?}, gfn_count: {:?}",
gfn_start, gfn_count
);
debug!("Releasing pages: gfn_start: {gfn_start:x?}, gfn_count: {gfn_count:?}");
let gpa_start = gfn_start * HV_PAGE_SIZE as u64;
for i in 0..gfn_count {
gpas.push(gpa_start + i * HV_PAGE_SIZE as u64);
@ -818,7 +814,7 @@ impl cpu::Vcpu for MshvVcpu {
self.vm_fd
.modify_gpa_host_access(&gpa_list[0])
.map_err(|e| cpu::HypervisorCpuError::RunVcpu(anyhow!(
"Unhandled VCPU exit: attribute intercept - couldn't modify host access {}", e
"Unhandled VCPU exit: attribute intercept - couldn't modify host access {e}"
)))?;
// Guest is revoking the shared access, so we need to update the bitmap
self.host_access_pages.rcu(|_bitmap| {
@ -835,9 +831,7 @@ impl cpu::Vcpu for MshvVcpu {
let gpa = info.guest_physical_address;
Err(cpu::HypervisorCpuError::RunVcpu(anyhow!(
"Unhandled VCPU exit: Unaccepted GPA({:x}) found at GVA({:x})",
gpa,
gva,
"Unhandled VCPU exit: Unaccepted GPA({gpa:x}) found at GVA({gva:x})",
)))
}
#[cfg(target_arch = "x86_64")]
@ -905,8 +899,7 @@ impl cpu::Vcpu for MshvVcpu {
<< GHCB_INFO_BIT_WIDTH)
as u64;
debug!(
"GHCB_INFO_HYP_FEATURE_REQUEST: Supported features: {:0x}",
ghcb_response
"GHCB_INFO_HYP_FEATURE_REQUEST: Supported features: {ghcb_response:0x}"
);
let arr_reg_name_value =
[(hv_register_name_HV_X64_REGISTER_GHCB, ghcb_response)];
@ -1182,8 +1175,7 @@ impl cpu::Vcpu for MshvVcpu {
.map_err(|e| cpu::HypervisorCpuError::RunVcpu(e.into()))?;
debug!(
"SNP guest request: req_gpa {:0x} rsp_gpa {:0x}",
req_gpa, rsp_gpa
"SNP guest request: req_gpa {req_gpa:0x} rsp_gpa {rsp_gpa:0x}"
);
set_svm_field_u64_ptr!(ghcb, exit_info2, 0);
@ -1194,8 +1186,7 @@ impl cpu::Vcpu for MshvVcpu {
let apic_id =
info.__bindgen_anon_2.__bindgen_anon_1.sw_exit_info1 >> 32;
debug!(
"SNP AP CREATE REQUEST with VMSA GPA {:0x}, and APIC ID {:?}",
vmsa_gpa, apic_id
"SNP AP CREATE REQUEST with VMSA GPA {vmsa_gpa:0x}, and APIC ID {apic_id:?}"
);
let mshv_ap_create_req = mshv_sev_snp_ap_create {
@ -1220,16 +1211,14 @@ impl cpu::Vcpu for MshvVcpu {
Ok(cpu::VmExit::Ignore)
}
exit => Err(cpu::HypervisorCpuError::RunVcpu(anyhow!(
"Unhandled VCPU exit {:?}",
exit
"Unhandled VCPU exit {exit:?}"
))),
},
Err(e) => match e.errno() {
libc::EAGAIN | libc::EINTR => Ok(cpu::VmExit::Ignore),
_ => Err(cpu::HypervisorCpuError::RunVcpu(anyhow!(
"VCPU error {:?}",
e
"VCPU error {e:?}"
))),
},
}
@ -1576,7 +1565,7 @@ impl MshvVcpu {
// SAFETY: Accessing a union element from bindgen generated bindings.
let prev_ghcb_gpa = unsafe { reg_assocs[0].value.reg64 };
debug!("Prev GHCB GPA is {:x}", prev_ghcb_gpa);
debug!("Prev GHCB GPA is {prev_ghcb_gpa:x}");
let mut ghcb_gpa = hv_x64_register_sev_ghcb::default();
@ -2224,7 +2213,7 @@ impl vm::Vm for MshvVm {
#[cfg(target_arch = "aarch64")]
fn create_vgic(&self, config: VgicConfig) -> vm::Result<Arc<Mutex<dyn Vgic>>> {
let gic_device = MshvGicV2M::new(self, config)
.map_err(|e| vm::HypervisorVmError::CreateVgic(anyhow!("Vgic error {:?}", e)))?;
.map_err(|e| vm::HypervisorVmError::CreateVgic(anyhow!("Vgic error {e:?}")))?;
// Register GICD address with the hypervisor
self.fd
@ -2233,7 +2222,7 @@ impl vm::Vm for MshvVm {
gic_device.dist_addr,
)
.map_err(|e| {
vm::HypervisorVmError::CreateVgic(anyhow!("Failed to set GICD address: {}", e))
vm::HypervisorVmError::CreateVgic(anyhow!("Failed to set GICD address: {e}"))
})?;
// Register GITS address with the hypervisor
@ -2244,7 +2233,7 @@ impl vm::Vm for MshvVm {
gic_device.gits_addr,
)
.map_err(|e| {
vm::HypervisorVmError::CreateVgic(anyhow!("Failed to set GITS address: {}", e))
vm::HypervisorVmError::CreateVgic(anyhow!("Failed to set GITS address: {e}"))
})?;
Ok(Arc::new(Mutex::new(gic_device)))
@ -2265,8 +2254,7 @@ impl vm::Vm for MshvVm {
)
.map_err(|e| {
vm::HypervisorVmError::SetVmProperty(anyhow!(
"Failed to set partition property: {}",
e
"Failed to set partition property: {e}"
))
})
}
@ -2281,8 +2269,7 @@ impl vm::Vm for MshvVm {
)
.map_err(|e| {
vm::HypervisorVmError::SetVmProperty(anyhow!(
"Failed to set partition property: {}",
e
"Failed to set partition property: {e}"
))
})
}
@ -2363,8 +2350,7 @@ impl vm::Vm for MshvVm {
)
.map_err(|e| {
vm::HypervisorVmError::InitializeVm(anyhow!(
"Failed to set GIC LPI support: {}",
e
"Failed to set GIC LPI support: {e}",
))
})?;
@ -2375,8 +2361,7 @@ impl vm::Vm for MshvVm {
)
.map_err(|e| {
vm::HypervisorVmError::InitializeVm(anyhow!(
"Failed to set arch timer interrupt ID: {}",
e
"Failed to set arch timer interrupt ID: {e}",
))
})?;
@ -2387,8 +2372,7 @@ impl vm::Vm for MshvVm {
)
.map_err(|e| {
vm::HypervisorVmError::InitializeVm(anyhow!(
"Failed to set PMU interrupt ID: {}",
e
"Failed to set PMU interrupt ID: {e}",
))
})?;
}

2
hypervisor/src/mshv/x86_64/emulator.rs
View file

@ -158,7 +158,7 @@ impl PlatformEmulator for MshvEmulatorContext<'_> {
.map_err(|e| PlatformError::GetCpuStateFailure(e.into()))?;
debug!("mshv emulator: Getting new CPU state");
debug!("mshv emulator: {:#x?}", regs);
debug!("mshv emulator: {regs:#x?}");
Ok(EmulatorCpuState { regs, sregs })
}

2
tracer/src/tracer.rs
View file

@ -52,7 +52,7 @@ impl Tracer {
file.flush().unwrap();
warn!("Trace output: {}", path);
warn!("Trace output: {path}");
}
fn add_event(&mut self, event: TraceEvent) {

2
vmm/src/api/mod.rs
View file

@ -757,7 +757,7 @@ impl ApiAction for VmCoredump {
response_sender: Sender<ApiResponse>,
) -> ApiRequest {
Box::new(move |vmm| {
info!("API request event: VmCoredump {:?}", coredump_data);
info!("API request event: VmCoredump {coredump_data:?}");
let response = vmm
.vm_coredump(&coredump_data.destination_url)

4
vmm/src/cpu.rs
View file

@ -1266,7 +1266,7 @@ impl CpuManager {
warn!("TDG_VP_VMCALL_SETUP_EVENT_NOTIFY_INTERRUPT not supported")
}
},
Err(e) => error!("Unexpected TDX VMCALL: {}", e),
Err(e) => error!("Unexpected TDX VMCALL: {e}"),
}
vcpu.vcpu.set_tdx_status(TdxExitStatus::InvalidOperand);
}
@ -1922,7 +1922,7 @@ impl CpuManager {
// or low (0x000xxx...).
let high_range = extract_bits_64!(gva, 55, 1);
if high_range == 0 {
info!("VA (0x{:x}) range is not supported!", gva);
info!("VA (0x{gva:x}) range is not supported!");
return Ok(gva);
}

6
vmm/src/device_manager.rs
View file

@ -3447,7 +3447,7 @@ impl DeviceManager {
let (pci_segment_id, pci_device_bdf, resources) =
self.pci_resources(&id, pci_segment_id)?;
info!("Creating pvmemcontrol device: id = {}", id);
info!("Creating pvmemcontrol device: id = {id}");
let (pvmemcontrol_pci_device, pvmemcontrol_bus_device) =
devices::pvmemcontrol::PvmemcontrolDevice::make_device(
id.clone(),
@ -4222,7 +4222,7 @@ impl DeviceManager {
) -> DeviceManagerResult<Option<Arc<Mutex<devices::IvshmemDevice>>>> {
let id = String::from(IVSHMEM_DEVICE_NAME);
let pci_segment_id = 0x0_u16;
info!("Creating ivshmem device {}", id);
info!("Creating ivshmem device {id}");
let (pci_segment_id, pci_device_bdf, resources) =
self.pci_resources(&id, pci_segment_id)?;
@ -4982,7 +4982,7 @@ impl IvshmemOps for IvshmemHandler {
size: usize,
backing_file: Option<PathBuf>,
) -> Result<(Arc<GuestRegionMmap>, UserspaceMapping), IvshmemError> {
info!("Creating ivshmem mem region at 0x{:x}", start_addr);
info!("Creating ivshmem mem region at 0x{start_addr:x}");
let region = MemoryManager::create_ram_region(
&backing_file,

32
vmm/src/gdb.rs
View file

@ -223,11 +223,11 @@ impl MultiThreadBase for GdbStub {
Ok(())
}
Ok(s) => {
error!("Unexpected response for ReadRegs: {:?}", s);
error!("Unexpected response for ReadRegs: {s:?}");
Err(TargetError::NonFatal)
}
Err(e) => {
error!("Failed to request ReadRegs: {:?}", e);
error!("Failed to request ReadRegs: {e:?}");
Err(TargetError::NonFatal)
}
}
@ -244,7 +244,7 @@ impl MultiThreadBase for GdbStub {
) {
Ok(_) => Ok(()),
Err(e) => {
error!("Failed to request WriteRegs: {:?}", e);
error!("Failed to request WriteRegs: {e:?}");
Err(TargetError::NonFatal)
}
}
@ -267,11 +267,11 @@ impl MultiThreadBase for GdbStub {
Ok(std::cmp::min(data.len(), r.len()))
}
Ok(s) => {
error!("Unexpected response for ReadMem: {:?}", s);
error!("Unexpected response for ReadMem: {s:?}");
Err(TargetError::NonFatal)
}
Err(e) => {
error!("Failed to request ReadMem: {:?}", e);
error!("Failed to request ReadMem: {e:?}");
Err(TargetError::NonFatal)
}
}
@ -289,7 +289,7 @@ impl MultiThreadBase for GdbStub {
) {
Ok(_) => Ok(()),
Err(e) => {
error!("Failed to request WriteMem: {:?}", e);
error!("Failed to request WriteMem: {e:?}");
Err(TargetError::NonFatal)
}
}
@ -414,7 +414,7 @@ impl HwBreakpoint for GdbStub {
match self.vm_request(payload, 0) {
Ok(_) => Ok(true),
Err(e) => {
error!("Failed to request SetHwBreakPoint: {:?}", e);
error!("Failed to request SetHwBreakPoint: {e:?}");
Err(TargetError::NonFatal)
}
}
@ -433,7 +433,7 @@ impl HwBreakpoint for GdbStub {
match self.vm_request(payload, 0) {
Ok(_) => Ok(true),
Err(e) => {
error!("Failed to request SetHwBreakPoint: {:?}", e);
error!("Failed to request SetHwBreakPoint: {e:?}");
Err(TargetError::NonFatal)
}
}
@ -498,7 +498,7 @@ impl run_blocking::BlockingEventLoop for GdbEventLoop {
target
.vm_request(GdbRequestPayload::Pause, 0)
.map_err(|e| {
error!("Failed to pause the target: {:?}", e);
error!("Failed to pause the target: {e:?}");
"Failed to pause the target"
})?;
Ok(Some(MultiThreadStopReason::Signal(Signal::SIGINT)))
@ -509,7 +509,7 @@ pub fn gdb_thread(mut gdbstub: GdbStub, path: &std::path::Path) {
let listener = match UnixListener::bind(path) {
Ok(s) => s,
Err(e) => {
error!("Failed to create a Unix domain socket listener: {}", e);
error!("Failed to create a Unix domain socket listener: {e}");
return;
}
};
@ -518,11 +518,11 @@ pub fn gdb_thread(mut gdbstub: GdbStub, path: &std::path::Path) {
let (stream, addr) = match listener.accept() {
Ok(v) => v,
Err(e) => {
error!("Failed to accept a connection from GDB: {}", e);
error!("Failed to accept a connection from GDB: {e}");
return;
}
};
info!("GDB connected from {:?}", addr);
info!("GDB connected from {addr:?}");
let connection: Box<dyn ConnectionExt<Error = std::io::Error>> = Box::new(stream);
let gdb = gdbstub::stub::GdbStub::new(connection);
@ -533,17 +533,17 @@ pub fn gdb_thread(mut gdbstub: GdbStub, path: &std::path::Path) {
info!("GDB client has disconnected. Running...");
if let Err(e) = gdbstub.vm_request(GdbRequestPayload::SetSingleStep(false), 0) {
error!("Failed to disable single step: {:?}", e);
error!("Failed to disable single step: {e:?}");
}
if let Err(e) =
gdbstub.vm_request(GdbRequestPayload::SetHwBreakPoint(Vec::new()), 0)
{
error!("Failed to remove breakpoints: {:?}", e);
error!("Failed to remove breakpoints: {e:?}");
}
if let Err(e) = gdbstub.vm_request(GdbRequestPayload::Resume, 0) {
error!("Failed to resume the VM: {:?}", e);
error!("Failed to resume the VM: {e:?}");
}
}
_ => {
@ -551,7 +551,7 @@ pub fn gdb_thread(mut gdbstub: GdbStub, path: &std::path::Path) {
}
},
Err(e) => {
error!("error occurred in GDB session: {}", e);
error!("error occurred in GDB session: {e}");
}
}
}

2
vmm/src/interrupt.rs
View file

@ -219,7 +219,7 @@ impl InterruptSourceGroup for LegacyUserspaceInterruptGroup {
.lock()
.unwrap()
.service_irq(self.irq as usize)
.map_err(|e| io::Error::other(format!("failed to inject IRQ #{}: {:?}", self.irq, e)))
.map_err(|e| io::Error::other(format!("failed to inject IRQ #{}: {e:?}", self.irq)))
}
fn update(

2
vmm/src/lib.rs
View file

@ -945,7 +945,7 @@ impl Vmm {
})?;
#[cfg(feature = "guest_debug")]
let debug_evt = self.vm_debug_evt.try_clone().map_err(|e| {
MigratableError::MigrateReceive(anyhow!("Error cloning debug EventFd: {}", e))
MigratableError::MigrateReceive(anyhow!("Error cloning debug EventFd: {e}"))
})?;
let activate_evt = self.activate_evt.try_clone().map_err(|e| {
MigratableError::MigrateReceive(anyhow!("Error cloning activate EventFd: {e}"))

2
vmm/src/memory_manager.rs
View file

@ -2074,7 +2074,7 @@ impl MemoryManager {
}
}
debug!("coredump total bytes {}", total_bytes);
debug!("coredump total bytes {total_bytes}");
Ok(())
}

2
vmm/src/migration.rs
View file

@ -39,7 +39,7 @@ pub fn url_to_file(url: &str) -> std::result::Result<PathBuf, GuestDebuggableErr
let file: PathBuf = url
.strip_prefix("file://")
.ok_or_else(|| {
GuestDebuggableError::Coredump(anyhow!("Could not extract file from URL: {}", url))
GuestDebuggableError::Coredump(anyhow!("Could not extract file from URL: {url}"))
})
.map(|s| s.into())?;

7
vmm/src/vm.rs
View file

@ -2072,13 +2072,12 @@ impl Vm {
// No need to allocate if the section falls within guest RAM ranges
if boot_guest_memory.address_in_range(GuestAddress(section.address)) {
info!(
"Not allocating TDVF Section: {:x?} since it is already part of guest RAM",
section
"Not allocating TDVF Section: {section:x?} since it is already part of guest RAM"
);
continue;
}
info!("Allocating TDVF Section: {:x?}", section);
info!("Allocating TDVF Section: {section:x?}");
self.memory_manager
.lock()
.unwrap()
@ -2106,7 +2105,7 @@ impl Vm {
let mut payload_info = None;
let mut hob_offset = None;
for section in sections {
info!("Populating TDVF Section: {:x?}", section);
info!("Populating TDVF Section: {section:x?}");
match section.r#type {
TdvfSectionType::Bfv | TdvfSectionType::Cfv => {
info!("Copying section to guest memory");