From eac44e6af011d70219ab60e2e87a27effc46c926 Mon Sep 17 00:00:00 2001 From: Jinank Jain Date: Mon, 5 May 2025 03:55:09 +0000 Subject: [PATCH] arch: Extend FDT for GICv2M device for ARM64 on MSHV GICv2M requires two additional properties to be exposed via FDT: 1) Base SPI number and 2) Total number of SPIs. SPIs in general starts from 32 and goes upto 1019. But currently we are limiting the range to 96 as that should be good enough for any normal Linux guest to function. Signed-off-by: Jinank Jain --- arch/src/aarch64/fdt.rs | 13 ++++++++++--- arch/src/aarch64/layout.rs | 9 +++++++++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/src/aarch64/fdt.rs b/arch/src/aarch64/fdt.rs index 3c3270ca6..60748f937 100644 --- a/arch/src/aarch64/fdt.rs +++ b/arch/src/aarch64/fdt.rs @@ -21,8 +21,8 @@ use vm_memory::{Address, Bytes, GuestMemory, GuestMemoryError, GuestMemoryRegion use super::super::{DeviceType, GuestMemoryMmap, InitramfsConfig}; use super::layout::{ - IRQ_BASE, MEM_32BIT_DEVICES_SIZE, MEM_32BIT_DEVICES_START, MEM_PCI_IO_SIZE, MEM_PCI_IO_START, - PCI_HIGH_BASE, PCI_MMIO_CONFIG_SIZE_PER_SEGMENT, + GIC_V2M_COMPATIBLE, IRQ_BASE, MEM_32BIT_DEVICES_SIZE, MEM_32BIT_DEVICES_START, MEM_PCI_IO_SIZE, + MEM_PCI_IO_START, PCI_HIGH_BASE, PCI_MMIO_CONFIG_SIZE_PER_SEGMENT, SPI_BASE, SPI_NUM, }; use crate::{NumaNodes, PciSpaceInfo}; @@ -670,12 +670,19 @@ fn create_gic_node(fdt: &mut FdtWriter, gic_device: &Arc>) -> Fd if gic_device.lock().unwrap().msi_compatible() { let msic_node = fdt.begin_node("msic")?; - fdt.property_string("compatible", gic_device.lock().unwrap().msi_compatibility())?; + let msi_compatibility = gic_device.lock().unwrap().msi_compatibility().to_string(); + + fdt.property_string("compatible", msi_compatibility.as_str())?; fdt.property_null("msi-controller")?; fdt.property_u32("phandle", MSI_PHANDLE)?; let msi_reg_prop = gic_device.lock().unwrap().msi_properties(); fdt.property_array_u64("reg", &msi_reg_prop)?; fdt.end_node(msic_node)?; + + if msi_compatibility == GIC_V2M_COMPATIBLE { + fdt.property_u32("arm,msi-base-spi", SPI_BASE)?; + fdt.property_u32("arm,msi-num-spis", SPI_NUM)?; + } } fdt.end_node(intc_node)?; diff --git a/arch/src/aarch64/layout.rs b/arch/src/aarch64/layout.rs index 53bae80e5..dc2c74e39 100644 --- a/arch/src/aarch64/layout.rs +++ b/arch/src/aarch64/layout.rs @@ -138,3 +138,12 @@ pub const IRQ_BASE: u32 = 32; /// Number of supported interrupts pub const IRQ_NUM: u32 = 256; + +/// Base SPI interrupt number +pub const SPI_BASE: u32 = 32; + +/// Total number of SPIs +pub const SPI_NUM: u32 = 64; + +/// GICv2M compatible string +pub const GIC_V2M_COMPATIBLE: &str = "arm,gic-v2m-frame";