devices: Implement DMA for fw_cfg device
We pass a reference to the guest memory when we create the device in DeviceManager. This allows us to access the guest memory for DMA. Signed-off-by: Alex Orozco <alexorozco@google.com>
This commit is contained in:
Alex Orozco
Bo Chen
parent
1f51e4525b
commit
edee53ac1a
4 changed files with 257 additions and 16 deletions
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@ -8,6 +8,7 @@ version = "0.1.0"
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acpi_tables = { workspace = true }
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anyhow = { workspace = true }
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arch = { path = "../arch" }
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bitfield-struct = { version = "0.10.1", optional = true }
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bitflags = { workspace = true }
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byteorder = { workspace = true }
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event_monitor = { path = "../event_monitor" }
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@ -43,6 +44,6 @@ arch = { path = "../arch" }
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[features]
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default = []
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fw_cfg = ["linux-loader", "zerocopy"]
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fw_cfg = ["bitfield-struct", "linux-loader", "zerocopy"]
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kvm = ["arch/kvm"]
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pvmemcontrol = []
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@ -13,7 +13,7 @@
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/// only firmware must implement mechanism to interact with this fw_cfg device
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use std::{
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fs::File,
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io::Result,
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io::{ErrorKind, Read, Result, Seek, SeekFrom},
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mem::offset_of,
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os::unix::fs::FileExt,
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sync::{Arc, Barrier},
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@ -30,16 +30,18 @@ use arch::layout::{
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MEM_32BIT_RESERVED_START, PCI_MMCONFIG_SIZE, PCI_MMCONFIG_START, RAM_64BIT_START,
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};
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use arch::RegionType;
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use bitfield_struct::bitfield;
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#[cfg(target_arch = "x86_64")]
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use linux_loader::bootparam::boot_params;
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#[cfg(target_arch = "aarch64")]
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use linux_loader::loader::pe::arm64_image_header as boot_params;
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use vm_device::BusDevice;
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use vm_memory::ByteValued;
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#[cfg(target_arch = "x86_64")]
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use vm_memory::GuestAddress;
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use vm_memory::bitmap::AtomicBitmap;
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use vm_memory::{
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ByteValued, Bytes, GuestAddress, GuestAddressSpace, GuestMemoryAtomic, GuestMemoryMmap,
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};
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use vmm_sys_util::sock_ctrl_msg::IntoIovec;
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use zerocopy::{FromBytes, Immutable, IntoBytes};
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use zerocopy::{FromBytes, FromZeros, Immutable, IntoBytes};
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#[cfg(target_arch = "x86_64")]
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// https://github.com/project-oak/oak/tree/main/stage0_bin#memory-layout
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@ -114,6 +116,34 @@ pub enum FwCfgContent {
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U32(u32),
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}
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struct FwCfgContentAccess<'a> {
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content: &'a FwCfgContent,
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offset: u32,
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}
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impl Read for FwCfgContentAccess<'_> {
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fn read(&mut self, buf: &mut [u8]) -> Result<usize> {
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match self.content {
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FwCfgContent::File(offset, f) => {
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Seek::seek(&mut (&*f), SeekFrom::Start(offset + self.offset as u64))?;
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Read::read(&mut (&*f), buf)
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}
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FwCfgContent::Bytes(b) => match b.get(self.offset as usize..) {
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Some(mut s) => s.read(buf),
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None => Err(ErrorKind::UnexpectedEof)?,
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},
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FwCfgContent::Slice(b) => match b.get(self.offset as usize..) {
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Some(mut s) => s.read(buf),
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None => Err(ErrorKind::UnexpectedEof)?,
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},
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FwCfgContent::U32(n) => match n.to_le_bytes().get(self.offset as usize..) {
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Some(mut s) => s.read(buf),
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None => Err(ErrorKind::UnexpectedEof)?,
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},
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}
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}
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}
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impl Default for FwCfgContent {
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fn default() -> Self {
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FwCfgContent::Slice(&[])
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@ -130,6 +160,12 @@ impl FwCfgContent {
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};
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u32::try_from(ret).map_err(|_| std::io::ErrorKind::InvalidInput.into())
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}
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fn access(&self, offset: u32) -> FwCfgContentAccess<'_> {
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FwCfgContentAccess {
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content: self,
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offset,
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}
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}
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}
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#[derive(Debug, Default)]
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@ -139,12 +175,45 @@ pub struct FwCfgItem {
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}
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/// https://www.qemu.org/docs/master/specs/fw_cfg.html
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#[derive(Debug, Default)]
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#[derive(Debug)]
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pub struct FwCfg {
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selector: u16,
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data_offset: u32,
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dma_address: u64,
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items: Vec<FwCfgItem>, // 0x20 and above
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known_items: [FwCfgContent; FW_CFG_KNOWN_ITEMS], // 0x0 to 0x19
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memory: GuestMemoryAtomic<GuestMemoryMmap<AtomicBitmap>>,
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}
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#[repr(C)]
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#[derive(Debug, IntoBytes, FromBytes)]
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struct FwCfgDmaAccess {
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control_be: u32,
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length_be: u32,
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address_be: u64,
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}
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// https://github.com/torvalds/linux/blob/master/include/uapi/linux/qemu_fw_cfg.h#L67
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#[bitfield(u32)]
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struct AccessControl {
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// FW_CFG_DMA_CTL_ERROR = 0x01
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error: bool,
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// FW_CFG_DMA_CTL_READ = 0x02
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read: bool,
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#[bits(1)]
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_unused2: u8,
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// FW_CFG_DMA_CTL_SKIP = 0x04
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skip: bool,
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#[bits(3)]
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_unused3: u8,
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// FW_CFG_DMA_CTL_ERROR = 0x08
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select: bool,
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#[bits(7)]
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_unused4: u8,
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// FW_CFG_DMA_CTL_WRITE = 0x10
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write: bool,
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#[bits(16)]
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_unused: u32,
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}
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#[repr(C)]
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@ -344,7 +413,7 @@ fn create_acpi_loader(acpi_table: AcpiTable) -> [FwCfgItem; 3] {
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}
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impl FwCfg {
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pub fn new() -> FwCfg {
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pub fn new(memory: GuestMemoryAtomic<GuestMemoryMmap<AtomicBitmap>>) -> FwCfg {
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const DEFAULT_ITEM: FwCfgContent = FwCfgContent::Slice(&[]);
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let mut known_items = [DEFAULT_ITEM; FW_CFG_KNOWN_ITEMS];
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known_items[FW_CFG_SIGNATURE as usize] = FwCfgContent::Slice(&FW_CFG_DMA_SIGNATURE);
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@ -355,8 +424,10 @@ impl FwCfg {
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FwCfg {
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selector: 0,
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data_offset: 0,
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dma_address: 0,
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items: vec![],
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known_items,
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memory,
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}
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}
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@ -448,6 +519,87 @@ impl FwCfg {
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Ok(())
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}
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fn dma_read_content(
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&self,
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content: &FwCfgContent,
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offset: u32,
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len: u32,
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address: u64,
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) -> Result<u32> {
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let content_size = content.size()?.saturating_sub(offset);
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let op_size = std::cmp::min(content_size, len);
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let mut access = content.access(offset);
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let mut buf = vec![0u8; op_size as usize];
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access.read_exact(buf.as_mut_bytes())?;
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let r = self
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.memory
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.memory()
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.write(buf.as_bytes(), GuestAddress(address));
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match r {
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Err(e) => {
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error!("fw_cfg: dma read error: {e:x?}");
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Err(ErrorKind::InvalidInput.into())
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}
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Ok(size) => Ok(size as u32),
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}
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}
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fn dma_read(&mut self, selector: u16, len: u32, address: u64) -> Result<()> {
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let op_size = if let Some(content) = self.known_items.get(selector as usize) {
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self.dma_read_content(content, self.data_offset, len, address)
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} else if let Some(item) = self.items.get((selector - FW_CFG_FILE_FIRST) as usize) {
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self.dma_read_content(&item.content, self.data_offset, len, address)
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} else {
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error!("fw_cfg: selector {selector:#x} does not exist.");
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Err(ErrorKind::NotFound.into())
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}?;
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self.data_offset += op_size;
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Ok(())
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}
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fn do_dma(&mut self) {
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let dma_address = self.dma_address;
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let mut access = FwCfgDmaAccess::new_zeroed();
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let dma_access = match self
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.memory
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.memory()
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.read(access.as_mut_bytes(), GuestAddress(dma_address))
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{
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Ok(_) => access,
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Err(e) => {
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error!("fw_cfg: invalid address of dma access {dma_address:#x}: {e:?}");
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return;
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}
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};
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let control = AccessControl(u32::from_be(dma_access.control_be));
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if control.select() {
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self.selector = control.select() as u16;
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}
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let len = u32::from_be(dma_access.length_be);
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let addr = u64::from_be(dma_access.address_be);
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let ret = if control.read() {
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self.dma_read(self.selector, len, addr)
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} else if control.write() {
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Err(ErrorKind::InvalidInput.into())
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} else if control.skip() {
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self.data_offset += len;
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Ok(())
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} else {
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Err(ErrorKind::InvalidData.into())
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};
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let mut access_resp = AccessControl(0);
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if let Err(e) = ret {
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error!("fw_cfg: dma operation {dma_access:x?}: {e:x?}");
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access_resp.set_error(true);
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}
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if let Err(e) = self.memory.memory().write(
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&access_resp.0.to_be_bytes(),
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GuestAddress(dma_address + core::mem::offset_of!(FwCfgDmaAccess, control_be) as u64),
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) {
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error!("fw_cfg: finishing dma: {e:?}")
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}
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}
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pub fn add_kernel_data(&mut self, file: &File) -> Result<()> {
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let mut buffer = vec![0u8; size_of::<boot_params>()];
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file.read_exact_at(&mut buffer, 0)?;
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@ -560,10 +712,14 @@ impl BusDevice for FwCfg {
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}
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(PORT_FW_CFG_DATA, _) => _ = self.read_data(data, size as u32),
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(PORT_FW_CFG_DMA_HI, 4) => {
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unimplemented!()
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let addr = self.dma_address;
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let addr_hi = (addr >> 32) as u32;
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data.copy_from_slice(&addr_hi.to_be_bytes());
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}
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(PORT_FW_CFG_DMA_LO, 4) => {
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unimplemented!()
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let addr = self.dma_address;
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let addr_lo = (addr & 0xffff_ffff) as u32;
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data.copy_from_slice(&addr_lo.to_be_bytes());
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}
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_ => {
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debug!("fw_cfg: read from unknown port {port:#x}: {size:#x} bytes and offset {offset:#x}.");
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@ -587,10 +743,19 @@ impl BusDevice for FwCfg {
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}
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(PORT_FW_CFG_DATA, 1) => error!("fw_cfg: data register is read-only."),
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(PORT_FW_CFG_DMA_HI, 4) => {
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unimplemented!()
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let mut buf = [0u8; 4];
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buf[..size].copy_from_slice(&data[..size]);
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let val = u32::from_be_bytes(buf);
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self.dma_address &= 0xffff_ffff;
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self.dma_address |= (val as u64) << 32;
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}
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(PORT_FW_CFG_DMA_LO, 4) => {
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unimplemented!()
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let mut buf = [0u8; 4];
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buf[..size].copy_from_slice(&data[..size]);
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let val = u32::from_be_bytes(buf);
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self.dma_address &= !0xffff_ffff;
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self.dma_address |= val as u64;
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self.do_dma();
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}
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_ => debug!(
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"fw_cfg: write to unknown port {port:#x}: {size:#x} bytes and offset {offset:#x} ."
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@ -617,10 +782,18 @@ mod tests {
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const DATA_OFFSET: u64 = 1;
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#[cfg(target_arch = "aarch64")]
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const DATA_OFFSET: u64 = 0;
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#[cfg(target_arch = "x86_64")]
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const DMA_OFFSET: u64 = 4;
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#[cfg(target_arch = "aarch64")]
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const DMA_OFFSET: u64 = 16;
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#[test]
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fn test_signature() {
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let mut fw_cfg = FwCfg::new();
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let gm = GuestMemoryAtomic::new(
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GuestMemoryMmap::from_ranges(&[(GuestAddress(0), RAM_64BIT_START.0 as usize)]).unwrap(),
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);
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let mut fw_cfg = FwCfg::new(gm);
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let mut data = vec![0u8];
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@ -637,7 +810,11 @@ mod tests {
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}
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#[test]
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fn test_kernel_cmdline() {
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let mut fw_cfg = FwCfg::new();
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let gm = GuestMemoryAtomic::new(
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GuestMemoryMmap::from_ranges(&[(GuestAddress(0), RAM_64BIT_START.0 as usize)]).unwrap(),
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);
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let mut fw_cfg = FwCfg::new(gm);
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let cmdline = *b"cmdline\0";
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@ -659,7 +836,11 @@ mod tests {
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#[test]
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fn test_initram_fs() {
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let mut fw_cfg = FwCfg::new();
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let gm = GuestMemoryAtomic::new(
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GuestMemoryMmap::from_ranges(&[(GuestAddress(0), RAM_64BIT_START.0 as usize)]).unwrap(),
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);
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let mut fw_cfg = FwCfg::new(gm);
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let temp = TempFile::new().unwrap();
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let mut temp_file = temp.as_file();
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@ -682,4 +863,60 @@ mod tests {
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}
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}
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}
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#[test]
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fn test_dma() {
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let code = [
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0xba, 0xf8, 0x03, 0x00, 0xd8, 0x04, b'0', 0xee, 0xb0, b'\n', 0xee, 0xf4,
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];
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let content = FwCfgContent::Bytes(code.to_vec());
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let mem_size = 0x1000;
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let load_addr = GuestAddress(0x1000);
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let mem: GuestMemoryMmap<AtomicBitmap> =
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GuestMemoryMmap::from_ranges(&[(load_addr, mem_size)]).unwrap();
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// Note: In firmware we would just allocate FwCfgDmaAccess struct
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// and use address of struct (&) as dma address
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let mut access_control = AccessControl(0);
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// bit 1 = read access
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access_control.set_read(true);
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// length of data to access
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let length_be = (code.len() as u32).to_be();
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// guest address for data
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let code_address = 0x1900_u64;
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let address_be = code_address.to_be();
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let mut access = FwCfgDmaAccess {
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control_be: access_control.0.to_be(), // bit(1) = read bit
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length_be,
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address_be,
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};
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// access address is where to put the code
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let access_address = GuestAddress(load_addr.0);
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let address_bytes = access_address.0.to_be_bytes();
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let dma_lo: [u8; 4] = address_bytes[0..4].try_into().unwrap();
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let dma_hi: [u8; 4] = address_bytes[4..8].try_into().unwrap();
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// writing the FwCfgDmaAccess to mem (this would just be self.dma_access.as_ref() in guest)
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let _ = mem.write(access.as_mut_bytes(), access_address);
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let mem_m = GuestMemoryAtomic::new(mem.clone());
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let mut fw_cfg = FwCfg::new(mem_m);
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let cfg_item = FwCfgItem {
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name: "code".to_string(),
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content,
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};
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let _ = fw_cfg.add_item(cfg_item);
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let mut data = [0u8; 12];
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let _ = mem.read(&mut data, GuestAddress(code_address));
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assert_ne!(data, code);
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fw_cfg.write(0, SELECTOR_OFFSET, &[FW_CFG_FILE_FIRST as u8, 0]);
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fw_cfg.write(0, DMA_OFFSET, &dma_lo);
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fw_cfg.write(0, DMA_OFFSET + 4, &dma_hi);
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let _ = mem.read(&mut data, GuestAddress(code_address));
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assert_eq!(data, code);
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}
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}
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