Ruoqing He 8cd80ea36b hypervisor: Introduce RISC-V architecture ... Introduce cpu, vm, kvm, arch module RISC-V platform support. Add macro definitions to implement methods interacting with RISC-V registers. Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>		2024-11-06 14:32:39 +00:00
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arch	hypervisor: arch: Integrate riscv64 to arch module	2024-11-06 14:32:39 +00:00
kvm	hypervisor: kvm: Integrate riscv64 regs & AIA	2024-11-06 14:32:39 +00:00
mshv	hypervisor: mshv: Fix superflous lifetimes	2024-10-21 15:28:17 +00:00
cpu.rs	hypervisor: cpu: Introduce RISC-V Vcpu trait	2024-11-06 14:32:39 +00:00
device.rs	hypervisor, vmm: use new vfio-ioctls	2022-07-21 23:37:53 +01:00
hypervisor.rs	misc: Adapt consistent import style formatting	2024-09-29 13:08:12 +01:00
lib.rs	hypervisor: Introduce RISC-V architecture	2024-11-06 14:32:39 +00:00
vm.rs	hypervisor: vm: Introduce RISC-V Vm trait	2024-11-06 14:32:39 +00:00