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pan/bi: Handle varying layout mismatches in emit_load_vary()

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If we're going to use the varying layout from the VS for the FS then we
need to be able to handle minor mismatches.  Mostly, this just means we
need to drop the assert that the set of locations matches 1:1.  We'll
use the byte offsets from the varying layout when we have one but keep
using the resource handles the driver put in driver_location for
LD_VAR[_IMM].

Reviewed-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38681>
This commit is contained in:
Faith Ekstrand 2025-12-04 00:56:41 -05:00 • committed by Marge Bot
parent 06d3c739c7
commit 0c8307d249
1 changed files with 3 additions and 4 deletions
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7
src/panfrost/compiler/bifrost/bifrost_compile.c
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@ -601,9 +601,6 @@ bi_emit_load_vary(bi_builder *b, nir_intrinsic_instr *instr)
if (b->shader->varying_layout) {
slot = pan_varying_layout_find_slot(b->shader->varying_layout,
sem.location);
ASSERTED uint32_t res_index =
pan_res_handle_get_index(nir_intrinsic_base(instr));
assert(slot == &b->shader->varying_layout->slots[res_index]);
}
unsigned sz = instr->def.bit_size;
@ -6613,7 +6610,9 @@ bi_compile_variant_nir(nir_shader *nir,
* problem as it's handled by the descriptor layout. However, for direct
* loads and stores on Valhall+, we need the right bit sizes in the shader.
* We could do this in the back-end as we emit but it's easier for now to
* lower in NIR.
* lower in NIR. This also handles the case where we do a load from the
* fragment shader of something that isn't written by the vertex shader.
* In that case, we just return zero.
*/
if (ctx->arch >= 9 && ctx->varying_layout) {
NIR_PASS(_, nir, pan_nir_resize_varying_io, ctx->varying_layout);