diff --git a/include/CL/cl.h b/include/CL/cl.h index d557720194f..4ec705dfc16 100644 --- a/include/CL/cl.h +++ b/include/CL/cl.h @@ -139,11 +139,11 @@ typedef struct _cl_image_desc { size_t image_slice_pitch; cl_uint num_mip_levels; cl_uint num_samples; -#if defined(CL_VERSION_2_0) && __CL_HAS_ANON_STRUCT__ - __CL_ANON_STRUCT__ union { +#if defined(CL_VERSION_2_0) && __CL_HAS_ANON_UNION__ + __CL_ANON_UNION__ union { #endif cl_mem buffer; -#if defined(CL_VERSION_2_0) && __CL_HAS_ANON_STRUCT__ +#if defined(CL_VERSION_2_0) && __CL_HAS_ANON_UNION__ cl_mem mem_object; }; #endif diff --git a/include/CL/cl_ext.h b/include/CL/cl_ext.h index f6c7fe5ffd8..8858b2b9269 100644 --- a/include/CL/cl_ext.h +++ b/include/CL/cl_ext.h @@ -54,7 +54,7 @@ extern "C" { "cl_khr_command_buffer" -#define CL_KHR_COMMAND_BUFFER_EXTENSION_VERSION CL_MAKE_VERSION(0, 9, 7) +#define CL_KHR_COMMAND_BUFFER_EXTENSION_VERSION CL_MAKE_VERSION(0, 9, 8) typedef cl_bitfield cl_device_command_buffer_capabilities_khr; typedef struct _cl_command_buffer_khr* cl_command_buffer_khr; @@ -74,14 +74,10 @@ typedef struct _cl_mutable_command_khr* cl_mutable_command_khr; /* cl_device_command_buffer_capabilities_khr - bitfield */ #define CL_COMMAND_BUFFER_CAPABILITY_KERNEL_PRINTF_KHR (1 << 0) #define CL_COMMAND_BUFFER_CAPABILITY_DEVICE_SIDE_ENQUEUE_KHR (1 << 1) -#define CL_COMMAND_BUFFER_CAPABILITY_SIMULTANEOUS_USE_KHR (1 << 2) /* cl_command_buffer_properties_khr */ #define CL_COMMAND_BUFFER_FLAGS_KHR 0x1293 -/* cl_command_buffer_flags_khr - bitfield */ -#define CL_COMMAND_BUFFER_SIMULTANEOUS_USE_KHR (1 << 0) - /* Error codes */ #define CL_INVALID_COMMAND_BUFFER_KHR -1138 #define CL_INVALID_SYNC_POINT_WAIT_LIST_KHR -1139 @@ -98,7 +94,6 @@ typedef struct _cl_mutable_command_khr* cl_mutable_command_khr; /* cl_command_buffer_state_khr */ #define CL_COMMAND_BUFFER_STATE_RECORDING_KHR 0 #define CL_COMMAND_BUFFER_STATE_EXECUTABLE_KHR 1 -#define CL_COMMAND_BUFFER_STATE_PENDING_KHR 2 /* cl_command_type */ #define CL_COMMAND_COMMAND_BUFFER_KHR 0x12A8 @@ -633,7 +628,7 @@ clRemapCommandBufferKHR( "cl_khr_command_buffer_mutable_dispatch" -#define CL_KHR_COMMAND_BUFFER_MUTABLE_DISPATCH_EXTENSION_VERSION CL_MAKE_VERSION(0, 9, 3) +#define CL_KHR_COMMAND_BUFFER_MUTABLE_DISPATCH_EXTENSION_VERSION CL_MAKE_VERSION(0, 9, 5) typedef cl_uint cl_command_buffer_update_type_khr; typedef cl_bitfield cl_mutable_dispatch_fields_khr; @@ -664,8 +659,12 @@ typedef struct _cl_mutable_dispatch_config_khr { typedef cl_bitfield cl_mutable_dispatch_asserts_khr; /* cl_command_buffer_flags_khr - bitfield */ +#define CL_COMMAND_BUFFER_SIMULTANEOUS_USE_KHR (1 << 0) #define CL_COMMAND_BUFFER_MUTABLE_KHR (1 << 1) +/* cl_device_command_buffer_capabilities_khr - bitfield */ +#define CL_COMMAND_BUFFER_CAPABILITY_SIMULTANEOUS_USE_KHR (1 << 2) + /* Error codes */ #define CL_INVALID_MUTABLE_COMMAND_KHR -1141 @@ -746,6 +745,9 @@ clGetMutableCommandInfoKHR( #endif /* !defined(CL_NO_NON_ICD_DISPATCH_EXTENSION_PROTOTYPES) */ +/* cl_command_buffer_state_khr */ +#define CL_COMMAND_BUFFER_STATE_FINALIZED_KHR 2 + #endif /* defined(CL_ENABLE_BETA_EXTENSIONS) */ /*************************************************************** @@ -3186,7 +3188,7 @@ typedef cl_bitfield cl_diagnostic_verbose_level_intel; "cl_intel_unified_shared_memory" -#define CL_INTEL_UNIFIED_SHARED_MEMORY_EXTENSION_VERSION CL_MAKE_VERSION(0, 0, 0) +#define CL_INTEL_UNIFIED_SHARED_MEMORY_EXTENSION_VERSION CL_MAKE_VERSION(1, 1, 0) typedef cl_bitfield cl_device_unified_shared_memory_capabilities_intel; typedef cl_properties cl_mem_properties_intel; @@ -4012,6 +4014,23 @@ clSetContentSizeBufferPoCL( #define CL_KHR_EXTENDED_BIT_OPS_EXTENSION_VERSION CL_MAKE_VERSION(1, 0, 0) +/*************************************************************** +* cl_khr_external_memory_android_hardware_buffer (beta) +***************************************************************/ +#if defined(CL_ENABLE_BETA_EXTENSIONS) + +#define cl_khr_external_memory_android_hardware_buffer 1 +#define CL_KHR_EXTERNAL_MEMORY_ANDROID_HARDWARE_BUFFER_EXTENSION_NAME \ + "cl_khr_external_memory_android_hardware_buffer" + + +#define CL_KHR_EXTERNAL_MEMORY_ANDROID_HARDWARE_BUFFER_EXTENSION_VERSION CL_MAKE_VERSION(0, 9, 2) + +/* cl_external_memory_handle_type_khr */ +#define CL_EXTERNAL_MEMORY_HANDLE_ANDROID_HARDWARE_BUFFER_KHR 0x2070 + +#endif /* defined(CL_ENABLE_BETA_EXTENSIONS) */ + /*************************************************************** * cl_khr_global_int32_base_atomics ***************************************************************/ @@ -4247,6 +4266,222 @@ typedef cl_bitfield cl_device_kernel_clock_capabilities_khr; #define CL_KHR_SUBGROUP_SHUFFLE_RELATIVE_EXTENSION_VERSION CL_MAKE_VERSION(1, 0, 0) +/*************************************************************** +* cl_khr_unified_svm (beta) +***************************************************************/ +#if defined(CL_ENABLE_BETA_EXTENSIONS) + +#if defined(CL_VERSION_2_0) + +#define cl_khr_unified_svm 1 +#define CL_KHR_UNIFIED_SVM_EXTENSION_NAME \ + "cl_khr_unified_svm" + + +#define CL_KHR_UNIFIED_SVM_EXTENSION_VERSION CL_MAKE_VERSION(0, 9, 0) + +/* cl_platform_info */ +#define CL_PLATFORM_SVM_TYPE_CAPABILITIES_KHR 0x0909 + +/* cl_device_info */ +#define CL_DEVICE_SVM_TYPE_CAPABILITIES_KHR 0x1077 + +typedef cl_bitfield cl_svm_capabilities_khr; + +/* cl_svm_capabilities_khr - bitfield */ +#define CL_SVM_CAPABILITY_SINGLE_ADDRESS_SPACE_KHR (1 << 0) +#define CL_SVM_CAPABILITY_SYSTEM_ALLOCATED_KHR (1 << 1) +#define CL_SVM_CAPABILITY_DEVICE_OWNED_KHR (1 << 2) +#define CL_SVM_CAPABILITY_DEVICE_UNASSOCIATED_KHR (1 << 3) +#define CL_SVM_CAPABILITY_CONTEXT_ACCESS_KHR (1 << 4) +#define CL_SVM_CAPABILITY_HOST_OWNED_KHR (1 << 5) +#define CL_SVM_CAPABILITY_HOST_READ_KHR (1 << 6) +#define CL_SVM_CAPABILITY_HOST_WRITE_KHR (1 << 7) +#define CL_SVM_CAPABILITY_HOST_MAP_KHR (1 << 8) +#define CL_SVM_CAPABILITY_DEVICE_READ_KHR (1 << 9) +#define CL_SVM_CAPABILITY_DEVICE_WRITE_KHR (1 << 10) +#define CL_SVM_CAPABILITY_DEVICE_ATOMIC_ACCESS_KHR (1 << 11) +#define CL_SVM_CAPABILITY_CONCURRENT_ACCESS_KHR (1 << 12) +#define CL_SVM_CAPABILITY_CONCURRENT_ATOMIC_ACCESS_KHR (1 << 13) +#define CL_SVM_CAPABILITY_INDIRECT_ACCESS_KHR (1 << 14) + +typedef cl_properties cl_svm_alloc_properties_khr; +typedef cl_bitfield cl_svm_alloc_access_flags_khr; +typedef cl_properties cl_svm_free_properties_khr; +typedef cl_bitfield cl_svm_free_flags_khr; +typedef cl_uint cl_svm_pointer_info_khr; + +/* cl_svm_alloc_properties_khr */ +#define CL_SVM_ALLOC_ASSOCIATED_DEVICE_HANDLE_KHR 0x2078 +#define CL_SVM_ALLOC_ACCESS_FLAGS_KHR 0x2079 +#define CL_SVM_ALLOC_ALIGNMENT_KHR 0x207A + +/* cl_svm_alloc_access_flags_khr */ +#define CL_SVM_ALLOC_ACCESS_HOST_NOREAD_KHR (1 << 0) +#define CL_SVM_ALLOC_ACCESS_HOST_NOWRITE_KHR (1 << 1) +#define CL_SVM_ALLOC_ACCESS_DEVICE_NOREAD_KHR (1 << 8) +#define CL_SVM_ALLOC_ACCESS_DEVICE_NOWRITE_KHR (1 << 9) + +/* cl_svm_pointer_info_khr */ +#define CL_SVM_INFO_TYPE_INDEX_KHR 0x2088 +#define CL_SVM_INFO_CAPABILITIES_KHR 0x2089 +#define CL_SVM_INFO_PROPERTIES_KHR 0x208A +#define CL_SVM_INFO_ACCESS_FLAGS_KHR 0x208B +#define CL_SVM_INFO_BASE_PTR_KHR 0x419B +#define CL_SVM_INFO_SIZE_KHR 0x419C +#define CL_SVM_INFO_ASSOCIATED_DEVICE_HANDLE_KHR 0x419D + +/* cl_kernel_exec_info */ +#define CL_KERNEL_EXEC_INFO_SVM_INDIRECT_ACCESS_KHR 0x11BB + +/* SVM type convenience macros */ +#define CL_SVM_TYPE_MACRO_COARSE_GRAIN_BUFFER_KHR \ + (CL_SVM_CAPABILITY_SINGLE_ADDRESS_SPACE_KHR | \ + CL_SVM_CAPABILITY_DEVICE_UNASSOCIATED_KHR | \ + CL_SVM_CAPABILITY_CONTEXT_ACCESS_KHR | \ + CL_SVM_CAPABILITY_HOST_MAP_KHR | \ + CL_SVM_CAPABILITY_DEVICE_READ_KHR | \ + CL_SVM_CAPABILITY_DEVICE_WRITE_KHR | \ + CL_SVM_CAPABILITY_DEVICE_ATOMIC_ACCESS_KHR) +#define CL_SVM_TYPE_MACRO_FINE_GRAIN_BUFFER_KHR \ + (CL_SVM_CAPABILITY_SINGLE_ADDRESS_SPACE_KHR | \ + CL_SVM_CAPABILITY_DEVICE_UNASSOCIATED_KHR | \ + CL_SVM_CAPABILITY_CONTEXT_ACCESS_KHR | \ + CL_SVM_CAPABILITY_HOST_READ_KHR | \ + CL_SVM_CAPABILITY_HOST_WRITE_KHR | \ + CL_SVM_CAPABILITY_HOST_MAP_KHR | \ + CL_SVM_CAPABILITY_DEVICE_READ_KHR | \ + CL_SVM_CAPABILITY_DEVICE_WRITE_KHR | \ + CL_SVM_CAPABILITY_DEVICE_ATOMIC_ACCESS_KHR | \ + CL_SVM_CAPABILITY_CONCURRENT_ACCESS_KHR) +#define CL_SVM_TYPE_MACRO_DEVICE_KHR \ + (CL_SVM_CAPABILITY_SINGLE_ADDRESS_SPACE_KHR | \ + CL_SVM_CAPABILITY_DEVICE_OWNED_KHR | \ + CL_SVM_CAPABILITY_DEVICE_READ_KHR | \ + CL_SVM_CAPABILITY_DEVICE_WRITE_KHR | \ + CL_SVM_CAPABILITY_DEVICE_ATOMIC_ACCESS_KHR | \ + CL_SVM_CAPABILITY_INDIRECT_ACCESS_KHR) +#define CL_SVM_TYPE_MACRO_HOST_KHR \ + (CL_SVM_CAPABILITY_SINGLE_ADDRESS_SPACE_KHR | \ + CL_SVM_CAPABILITY_DEVICE_UNASSOCIATED_KHR | \ + CL_SVM_CAPABILITY_CONTEXT_ACCESS_KHR | \ + CL_SVM_CAPABILITY_HOST_OWNED_KHR | \ + CL_SVM_CAPABILITY_HOST_READ_KHR | \ + CL_SVM_CAPABILITY_HOST_WRITE_KHR | \ + CL_SVM_CAPABILITY_DEVICE_READ_KHR | \ + CL_SVM_CAPABILITY_DEVICE_WRITE_KHR | \ + CL_SVM_CAPABILITY_INDIRECT_ACCESS_KHR) +#define CL_SVM_TYPE_MACRO_SINGLE_DEVICE_SHARED_KHR \ + (CL_SVM_CAPABILITY_SINGLE_ADDRESS_SPACE_KHR | \ + CL_SVM_CAPABILITY_HOST_READ_KHR | \ + CL_SVM_CAPABILITY_HOST_WRITE_KHR | \ + CL_SVM_CAPABILITY_DEVICE_READ_KHR | \ + CL_SVM_CAPABILITY_DEVICE_WRITE_KHR | \ + CL_SVM_CAPABILITY_INDIRECT_ACCESS_KHR) +#define CL_SVM_TYPE_MACRO_SYSTEM_KHR \ + (CL_SVM_CAPABILITY_SINGLE_ADDRESS_SPACE_KHR | \ + CL_SVM_CAPABILITY_SYSTEM_ALLOCATED_KHR | \ + CL_SVM_CAPABILITY_DEVICE_UNASSOCIATED_KHR | \ + CL_SVM_CAPABILITY_CONTEXT_ACCESS_KHR | \ + CL_SVM_CAPABILITY_HOST_READ_KHR | \ + CL_SVM_CAPABILITY_HOST_WRITE_KHR | \ + CL_SVM_CAPABILITY_HOST_MAP_KHR | \ + CL_SVM_CAPABILITY_DEVICE_READ_KHR | \ + CL_SVM_CAPABILITY_DEVICE_WRITE_KHR | \ + CL_SVM_CAPABILITY_DEVICE_ATOMIC_ACCESS_KHR | \ + CL_SVM_CAPABILITY_CONCURRENT_ACCESS_KHR | \ + CL_SVM_CAPABILITY_CONCURRENT_ATOMIC_ACCESS_KHR | \ + CL_SVM_CAPABILITY_INDIRECT_ACCESS_KHR) + + +typedef void* CL_API_CALL +clSVMAllocWithPropertiesKHR_t( + cl_context context, + const cl_svm_alloc_properties_khr* properties, + cl_uint svm_type_index, + size_t size, + cl_int* errcode_ret); + +typedef clSVMAllocWithPropertiesKHR_t * +clSVMAllocWithPropertiesKHR_fn ; + +typedef cl_int CL_API_CALL +clSVMFreeWithPropertiesKHR_t( + cl_context context, + const cl_svm_free_properties_khr* properties, + cl_svm_free_flags_khr flags, + void* ptr); + +typedef clSVMFreeWithPropertiesKHR_t * +clSVMFreeWithPropertiesKHR_fn ; + +typedef cl_int CL_API_CALL +clGetSVMPointerInfoKHR_t( + cl_context context, + cl_device_id device, + const void* ptr, + cl_svm_pointer_info_khr param_name, + size_t param_value_size, + void* param_value, + size_t* param_value_size_ret); + +typedef clGetSVMPointerInfoKHR_t * +clGetSVMPointerInfoKHR_fn ; + +typedef cl_int CL_API_CALL +clGetSVMSuggestedTypeIndexKHR_t( + cl_context context, + cl_svm_capabilities_khr required_capabilities, + cl_svm_capabilities_khr desired_capabilities, + const cl_svm_alloc_properties_khr* properties, + size_t size, + cl_uint* suggested_svm_type_index); + +typedef clGetSVMSuggestedTypeIndexKHR_t * +clGetSVMSuggestedTypeIndexKHR_fn ; + +#if !defined(CL_NO_NON_ICD_DISPATCH_EXTENSION_PROTOTYPES) + +extern CL_API_ENTRY void* CL_API_CALL +clSVMAllocWithPropertiesKHR( + cl_context context, + const cl_svm_alloc_properties_khr* properties, + cl_uint svm_type_index, + size_t size, + cl_int* errcode_ret) ; + +extern CL_API_ENTRY cl_int CL_API_CALL +clSVMFreeWithPropertiesKHR( + cl_context context, + const cl_svm_free_properties_khr* properties, + cl_svm_free_flags_khr flags, + void* ptr) ; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetSVMPointerInfoKHR( + cl_context context, + cl_device_id device, + const void* ptr, + cl_svm_pointer_info_khr param_name, + size_t param_value_size, + void* param_value, + size_t* param_value_size_ret) ; + +extern CL_API_ENTRY cl_int CL_API_CALL +clGetSVMSuggestedTypeIndexKHR( + cl_context context, + cl_svm_capabilities_khr required_capabilities, + cl_svm_capabilities_khr desired_capabilities, + const cl_svm_alloc_properties_khr* properties, + size_t size, + cl_uint* suggested_svm_type_index) ; + +#endif /* !defined(CL_NO_NON_ICD_DISPATCH_EXTENSION_PROTOTYPES) */ + +#endif /* defined(CL_VERSION_2_0) */ + +#endif /* defined(CL_ENABLE_BETA_EXTENSIONS) */ + /*************************************************************** * cl_khr_work_group_uniform_arithmetic ***************************************************************/ @@ -4373,6 +4608,56 @@ clCancelCommandsIMG( #endif /* !defined(CL_NO_NON_ICD_DISPATCH_EXTENSION_PROTOTYPES) */ +/*************************************************************** +* cl_img_safety_mechanisms +***************************************************************/ +#define cl_img_safety_mechanisms 1 +#define CL_IMG_SAFETY_MECHANISMS_EXTENSION_NAME \ + "cl_img_safety_mechanisms" + + +#define CL_IMG_SAFETY_MECHANISMS_EXTENSION_VERSION CL_MAKE_VERSION(1, 0, 0) + +/* cl_context_properties */ +#define CL_CONTEXT_SAFETY_PROPERTIES_IMG 0x40D9 + +/* Types */ +typedef cl_bitfield cl_context_safety_properties_img; + +/* cl_context_safety_properties_img */ +#define CL_CONTEXT_WORKGROUP_PROTECTION_IMG (1 << 0) +#define CL_CONTEXT_ENHANCED_EVENT_EXECUTION_STATUS_IMG (1 << 1) + +/* cl_device_info */ +#define CL_DEVICE_WORKGROUP_PROTECTION_SVM_CAPABILITIES_IMG 0x40DA +#define CL_DEVICE_WORKGROUP_PROTECTION_DEVICE_ENQUEUE_CAPABILITIES_IMG 0x40DB +#define CL_DEVICE_SAFETY_MEM_SIZE_IMG 0x40DC + +/* Error codes */ +#define CL_ECC_RECOVERED_IMG 0x40DD +#define CL_PAGE_FAULT_IMG -1127 +#define CL_SAFETY_FAULT_IMG -1128 +#define CL_GENERAL_FAULT_IMG -1129 +#define CL_ECC_UNRECOVERED_IMG -1130 + +/*************************************************************** +* cl_img_unified_svm_external_memory_dma_buf (beta) +***************************************************************/ +#if defined(CL_ENABLE_BETA_EXTENSIONS) + +#define cl_img_unified_svm_external_memory_dma_buf 1 +#define CL_IMG_UNIFIED_SVM_EXTERNAL_MEMORY_DMA_BUF_EXTENSION_NAME \ + "cl_img_unified_svm_external_memory_dma_buf" + + +#define CL_IMG_UNIFIED_SVM_EXTERNAL_MEMORY_DMA_BUF_EXTENSION_VERSION CL_MAKE_VERSION(1, 1, 0) + +/* cl_svm_alloc_properties_khr */ +#define CL_SVM_ALLOC_EXTERNAL_MEMORY_DMA_BUF_VIRTUAL_ADDRESS_IMG 0x4220 +#define CL_SVM_ALLOC_EXTERNAL_MEMORY_DMA_BUF_IMG 0x4221 + +#endif /* defined(CL_ENABLE_BETA_EXTENSIONS) */ + /*************************************************************** * cl_qcom_perf_hint ***************************************************************/ diff --git a/include/CL/cl_icd.h b/include/CL/cl_icd.h index bce60ea25b4..346ab5aa9a3 100644 --- a/include/CL/cl_icd.h +++ b/include/CL/cl_icd.h @@ -44,11 +44,11 @@ extern "C" { typedef struct _cl_icd_dispatch { /* OpenCL 1.0 */ -#if __CL_HAS_ANON_STRUCT__ - __CL_ANON_STRUCT__ union { +#if __CL_HAS_ANON_UNION__ + __CL_ANON_UNION__ union { #endif clGetPlatformIDs_t *clGetPlatformIDs; -#if __CL_HAS_ANON_STRUCT__ +#if __CL_HAS_ANON_UNION__ /* Set to CL_ICD2_TAG_KHR for cl_khr_icd 2.0.0 */ intptr_t clGetPlatformIDs_icd2_tag; }; @@ -83,11 +83,11 @@ typedef struct _cl_icd_dispatch { clRetainProgram_t *clRetainProgram; clReleaseProgram_t *clReleaseProgram; clBuildProgram_t *clBuildProgram; -#if __CL_HAS_ANON_STRUCT__ - __CL_ANON_STRUCT__ union { +#if __CL_HAS_ANON_UNION__ + __CL_ANON_UNION__ union { #endif clUnloadCompiler_t *clUnloadCompiler; -#if __CL_HAS_ANON_STRUCT__ +#if __CL_HAS_ANON_UNION__ /* Set to CL_ICD2_TAG_KHR for cl_khr_icd 2.0.0 */ intptr_t clUnloadCompiler_icd2_tag; }; diff --git a/include/CL/cl_platform.h b/include/CL/cl_platform.h index 5f92d6faad4..caf0ad04fa9 100644 --- a/include/CL/cl_platform.h +++ b/include/CL/cl_platform.h @@ -519,6 +519,16 @@ typedef double cl_double; #define __CL_ANON_STRUCT__ #endif +/* Define capabilities for anonymous union members. */ +#if defined(__cplusplus) && __cplusplus >= 201103L +#define __CL_HAS_ANON_UNION__ 1 +#define __CL_ANON_UNION__ +#else + /* Follow anonymous struct logic */ +#define __CL_HAS_ANON_UNION__ __CL_HAS_ANON_STRUCT__ +#define __CL_ANON_UNION__ __CL_ANON_STRUCT__ +#endif + #if defined(_WIN32) && defined(_MSC_VER) && __CL_HAS_ANON_STRUCT__ /* Disable warning C4201: nonstandard extension used : nameless struct/union */ #pragma warning( push ) diff --git a/include/CL_intel/cl_ext_private.h b/include/CL_intel/cl_ext_private.h new file mode 100644 index 00000000000..f4eca600c36 --- /dev/null +++ b/include/CL_intel/cl_ext_private.h @@ -0,0 +1,396 @@ +/* + * Copyright (C) 2018-2025 Intel Corporation + * + * SPDX-License-Identifier: MIT + * + */ + +#pragma once + +#include "CL/cl.h" +#include "CL/cl_ext.h" + +/********************************** + * Internal only queue properties * + **********************************/ +// Intel evaluation now. Remove it after approval for public release +#define CL_DEVICE_DRIVER_VERSION_INTEL 0x10010 + +#define CL_DEVICE_DRIVER_VERSION_INTEL_NEO1 0x454E4831 // Driver version is ENH1 + +/********************************************* + * Internal only kernel exec info properties * + *********************************************/ + +#define CL_KERNEL_EXEC_INFO_KERNEL_TYPE_INTEL 0x1000C +#define CL_KERNEL_EXEC_INFO_DEFAULT_TYPE_INTEL 0x1000D +#define CL_KERNEL_EXEC_INFO_CONCURRENT_TYPE_INTEL 0x1000E + +/********************************* + * cl_intel_debug_info extension * + *********************************/ +#define cl_intel_debug_info 1 + +// New queries for clGetProgramInfo: +#define CL_PROGRAM_DEBUG_INFO_INTEL 0x4100 +#define CL_PROGRAM_DEBUG_INFO_SIZES_INTEL 0x4101 + +// New queries for clGetKernelInfo: +#define CL_KERNEL_BINARY_PROGRAM_INTEL 0x407D +#define CL_KERNEL_BINARIES_INTEL 0x4102 +#define CL_KERNEL_BINARY_SIZES_INTEL 0x4103 +#define CL_KERNEL_BINARY_GPU_ADDRESS_INTEL 0x10010 + +/******************************************** + * event properties for performance counter * + ********************************************/ +/* performance counter */ +#define CL_PROFILING_COMMAND_PERFCOUNTERS_INTEL 0x407F + +/************************** + * Internal only cl types * + **************************/ + +using cl_execution_info_kernel_type_intel = cl_uint; +using cl_mem_flags_intel = cl_mem_flags; +using cl_unified_shared_memory_capabilities_intel = cl_bitfield; + +#if !defined(cl_intel_unified_shared_memory) +using cl_mem_alloc_flags_intel = cl_bitfield; +using cl_mem_properties_intel = cl_bitfield; +using cl_mem_info_intel = cl_uint; +using cl_mem_advice_intel = cl_uint; +using cl_unified_shared_memory_type_intel = cl_uint; +#endif + +/****************************** + * Internal only cl_mem_flags * + ******************************/ + +#define CL_MEM_FLAGS_INTEL 0x10001 +#define CL_MEM_LOCALLY_UNCACHED_RESOURCE (1 << 18) +#define CL_MEM_LOCALLY_UNCACHED_SURFACE_STATE_RESOURCE (1 << 25) +#define CL_MEM_48BIT_RESOURCE_INTEL (1 << 26) + +#define CL_MEM_DEVICE_ID_INTEL_DEPRECATED 0x10011 + +// Used with clEnqueueVerifyMemory +#define CL_MEM_COMPARE_EQUAL 0u +#define CL_MEM_COMPARE_NOT_EQUAL 1u + +#define CL_MEM_FORCE_LINEAR_STORAGE_INTEL (1 << 19) +#define CL_MEM_FORCE_HOST_MEMORY_INTEL (1 << 20) + +#define CL_MEM_ALLOCATION_HANDLE_INTEL 0x10050 +#define CL_MEM_USES_COMPRESSION_INTEL 0x10051 + +// Used with createBuffer +#define CL_MEM_ALLOW_UNRESTRICTED_SIZE_INTEL (1 << 23) + +/****************************** + * UNIFIED MEMORY * + *******************************/ + +#if !defined(cl_intel_unified_shared_memory) + +/* cl_device_info */ +#define CL_DEVICE_HOST_MEM_CAPABILITIES_INTEL 0x4190 +#define CL_DEVICE_DEVICE_MEM_CAPABILITIES_INTEL 0x4191 +#define CL_DEVICE_SINGLE_DEVICE_SHARED_MEM_CAPABILITIES_INTEL 0x4192 +#define CL_DEVICE_CROSS_DEVICE_SHARED_MEM_CAPABILITIES_INTEL 0x4193 +#define CL_DEVICE_SHARED_SYSTEM_MEM_CAPABILITIES_INTEL 0x4194 + +/* cl_unified_shared_memory_capabilities_intel - bitfield */ +#define CL_UNIFIED_SHARED_MEMORY_ACCESS_INTEL (1 << 0) +#define CL_UNIFIED_SHARED_MEMORY_ATOMIC_ACCESS_INTEL (1 << 1) +#define CL_UNIFIED_SHARED_MEMORY_CONCURRENT_ACCESS_INTEL (1 << 2) +#define CL_UNIFIED_SHARED_MEMORY_CONCURRENT_ATOMIC_ACCESS_INTEL (1 << 3) + +/* cl_mem_properties_intel */ +#define CL_MEM_ALLOC_FLAGS_INTEL 0x4195 +#define CL_MEM_ALLOC_USE_HOST_PTR_INTEL 0x1000F + +/* cl_mem_alloc_flags_intel - bitfield */ +#define CL_MEM_ALLOC_WRITE_COMBINED_INTEL (1 << 0) +#define CL_MEM_ALLOC_INITIAL_PLACEMENT_DEVICE_INTEL (1 << 1) +#define CL_MEM_ALLOC_INITIAL_PLACEMENT_HOST_INTEL (1 << 2) + +/* cl_mem_alloc_info_intel */ +#define CL_MEM_ALLOC_TYPE_INTEL 0x419A +#define CL_MEM_ALLOC_BASE_PTR_INTEL 0x419B +#define CL_MEM_ALLOC_SIZE_INTEL 0x419C +#define CL_MEM_ALLOC_DEVICE_INTEL 0x419D + +/* cl_unified_shared_memory_type_intel */ +#define CL_MEM_TYPE_UNKNOWN_INTEL 0x4196 +#define CL_MEM_TYPE_HOST_INTEL 0x4197 +#define CL_MEM_TYPE_DEVICE_INTEL 0x4198 +#define CL_MEM_TYPE_SHARED_INTEL 0x4199 + +/* cl_command_type */ +#define CL_COMMAND_MEMFILL_INTEL 0x4204 +#define CL_COMMAND_MEMCPY_INTEL 0x4205 +#define CL_COMMAND_MIGRATEMEM_INTEL 0x4206 +#define CL_COMMAND_MEMADVISE_INTEL 0x4207 + +#endif + +/* cl_mem_alloc_flags_intel - bitfield */ +#define CL_MEM_ALLOC_DEFAULT_INTEL 0 + +/* cl_mem_properties_intel */ +#define CL_MEM_ALLOC_USE_HOST_PTR_INTEL 0x1000F + +/* cl_command_type */ +#define CL_COMMAND_MEMSET_INTEL 0x4204 + +/****************************** + * THREAD ARBITRATION POLICY * + *******************************/ + +/* cl_device_info */ +#define CL_DEVICE_SUPPORTED_THREAD_ARBITRATION_POLICY_INTEL 0x4208 + +/* cl_kernel_exec_info */ +#if !defined(cl_intel_unified_shared_memory) +#define CL_KERNEL_EXEC_INFO_INDIRECT_HOST_ACCESS_INTEL 0x4200 +#define CL_KERNEL_EXEC_INFO_INDIRECT_DEVICE_ACCESS_INTEL 0x4201 +#define CL_KERNEL_EXEC_INFO_INDIRECT_SHARED_ACCESS_INTEL 0x4202 +#define CL_KERNEL_EXEC_INFO_USM_PTRS_INTEL 0x4203 +#endif + +#define CL_KERNEL_EXEC_INFO_THREAD_ARBITRATION_POLICY_OLDEST_FIRST_INTEL 0x10022 +#define CL_KERNEL_EXEC_INFO_THREAD_ARBITRATION_POLICY_ROUND_ROBIN_INTEL 0x10023 +#define CL_KERNEL_EXEC_INFO_THREAD_ARBITRATION_POLICY_AFTER_DEPENDENCY_ROUND_ROBIN_INTEL 0x10024 +#define CL_KERNEL_EXEC_INFO_THREAD_ARBITRATION_POLICY_INTEL 0x10025 +#define CL_KERNEL_EXEC_INFO_THREAD_ARBITRATION_POLICY_STALL_BASED_ROUND_ROBIN_INTEL 0x10026 + +/****************************** + * SLICE COUNT SELECTING * + *******************************/ + +/* cl_device_info */ +#define CL_DEVICE_SLICE_COUNT_INTEL 0x10020 + +/* cl_queue_properties */ +#define CL_QUEUE_SLICE_COUNT_INTEL 0x10021 + +/****************************** + * QUEUE FAMILY SELECTING * + *******************************/ + +#if !defined(cl_intel_command_queue_families) + +/* cl_device_info */ +#define CL_DEVICE_QUEUE_FAMILY_PROPERTIES_INTEL 0x418B + +/* cl_queue_properties */ +#define CL_QUEUE_FAMILY_INTEL 0x418C +#define CL_QUEUE_INDEX_INTEL 0x418D + +/* cl_command_queue_capabilities_intel */ +#define CL_QUEUE_DEFAULT_CAPABILITIES_INTEL 0 +#define CL_QUEUE_CAPABILITY_CREATE_SINGLE_QUEUE_EVENTS_INTEL (1 << 0) +#define CL_QUEUE_CAPABILITY_CREATE_CROSS_QUEUE_EVENTS_INTEL (1 << 1) +#define CL_QUEUE_CAPABILITY_SINGLE_QUEUE_EVENT_WAIT_LIST_INTEL (1 << 2) +#define CL_QUEUE_CAPABILITY_CROSS_QUEUE_EVENT_WAIT_LIST_INTEL (1 << 3) +#define CL_QUEUE_CAPABILITY_TRANSFER_BUFFER_INTEL (1 << 8) +#define CL_QUEUE_CAPABILITY_TRANSFER_BUFFER_RECT_INTEL (1 << 9) +#define CL_QUEUE_CAPABILITY_MAP_BUFFER_INTEL (1 << 10) +#define CL_QUEUE_CAPABILITY_FILL_BUFFER_INTEL (1 << 11) +#define CL_QUEUE_CAPABILITY_TRANSFER_IMAGE_INTEL (1 << 12) +#define CL_QUEUE_CAPABILITY_MAP_IMAGE_INTEL (1 << 13) +#define CL_QUEUE_CAPABILITY_FILL_IMAGE_INTEL (1 << 14) +#define CL_QUEUE_CAPABILITY_TRANSFER_BUFFER_IMAGE_INTEL (1 << 15) +#define CL_QUEUE_CAPABILITY_TRANSFER_IMAGE_BUFFER_INTEL (1 << 16) +#define CL_QUEUE_CAPABILITY_MARKER_INTEL (1 << 24) +#define CL_QUEUE_CAPABILITY_BARRIER_INTEL (1 << 25) +#define CL_QUEUE_CAPABILITY_KERNEL_INTEL (1 << 26) + +typedef cl_bitfield cl_command_queue_capabilities_intel; + +#define CL_QUEUE_FAMILY_MAX_NAME_SIZE_INTEL 64 +typedef struct _cl_queue_family_properties_intel { + cl_command_queue_properties properties; + cl_command_queue_capabilities_intel capabilities; + cl_uint count; + char name[CL_QUEUE_FAMILY_MAX_NAME_SIZE_INTEL]; +} cl_queue_family_properties_intel; + +#endif + +/****************************** + * DEVICE ATTRIBUTE QUERY * + *******************************/ + +#if !defined(cl_intel_device_attribute_query) + +/* For GPU devices, version 1.0.0: */ +#define CL_DEVICE_IP_VERSION_INTEL 0x4250 +#define CL_DEVICE_ID_INTEL 0x4251 +#define CL_DEVICE_NUM_SLICES_INTEL 0x4252 +#define CL_DEVICE_NUM_SUB_SLICES_PER_SLICE_INTEL 0x4253 +#define CL_DEVICE_NUM_EUS_PER_SUB_SLICE_INTEL 0x4254 +#define CL_DEVICE_NUM_THREADS_PER_EU_INTEL 0x4255 +#define CL_DEVICE_FEATURE_CAPABILITIES_INTEL 0x4256 + +typedef cl_bitfield cl_device_feature_capabilities_intel; + +/* For GPU devices, version 1.0.0: */ +#define CL_DEVICE_FEATURE_FLAG_DP4A_INTEL (1 << 0) +#define CL_DEVICE_FEATURE_FLAG_DPAS_INTEL (1 << 1) + +#endif + +////// RESOURCE BARRIER EXT +#define CL_COMMAND_RESOURCE_BARRIER 0x10010 + +typedef cl_uint cl_resource_barrier_type; +#define CL_RESOURCE_BARRIER_TYPE_ACQUIRE 0x1 // FLUSH+EVICT +#define CL_RESOURCE_BARRIER_TYPE_RELEASE 0x2 // FLUSH +#define CL_RESOURCE_BARRIER_TYPE_DISCARD 0x3 // DISCARD + +typedef cl_uint cl_resource_memory_scope; +#define CL_MEMORY_SCOPE_DEVICE 0x0 // INCLUDES CROSS-TILE +#define CL_MEMORY_SCOPE_ALL_SVM_DEVICES 0x1 // CL_MEMORY_SCOPE_DEVICE + CROSS-DEVICE + +#pragma pack(push, 1) +typedef struct _cl_resource_barrier_descriptor_intel { + void *svmAllocationPointer; + cl_mem memObject; + cl_resource_barrier_type type; + cl_resource_memory_scope scope; +} cl_resource_barrier_descriptor_intel; +#pragma pack(pop) + +/**************************************** + * cl_khr_pci_bus_info extension * + ***************************************/ + +#if !defined(cl_khr_pci_bus_info) + +#define cl_khr_pci_bus_info 1 + +// New queries for clGetDeviceInfo: +#define CL_DEVICE_PCI_BUS_INFO_KHR 0x410F + +typedef struct _cl_device_pci_bus_info_khr { + cl_uint pci_domain; + cl_uint pci_bus; + cl_uint pci_device; + cl_uint pci_function; +} cl_device_pci_bus_info_khr; + +#endif + +/************************************************ + * cl_intel_mem_compression_hints extension * + *************************************************/ +#define CL_MEM_COMPRESSED_HINT_INTEL (1u << 21) +#define CL_MEM_UNCOMPRESSED_HINT_INTEL (1u << 22) + +// New query for clGetDeviceInfo: +#define CL_MEM_COMPRESSED_INTEL 0x417D + +/* cl_queue_properties */ +#define CL_QUEUE_MDAPI_PROPERTIES_INTEL 0x425E +#define CL_QUEUE_MDAPI_CONFIGURATION_INTEL 0x425F + +typedef cl_bitfield cl_command_queue_mdapi_properties_intel; + +/* cl_command_queue_mdapi_properties_intel - bitfield */ +#define CL_QUEUE_MDAPI_ENABLE_INTEL (1 << 0) + +/************************************************ + * cl_khr_external_memory extension * + *************************************************/ + +#if !defined(cl_khr_external_memory) + +/* clGetPlatformInfo */ +#define CL_PLATFORM_EXTERNAL_MEMORY_IMPORT_HANDLE_TYPES_KHR 0x2044 + +/* clGetDeviceInfo */ +#define CL_DEVICE_EXTERNAL_MEMORY_IMPORT_HANDLE_TYPES_KHR 0x204F + +/* clCreateBufferWithProperties and clCreateImageWithProperties */ +#define CL_DEVICE_HANDLE_LIST_KHR 0x2051 +#define CL_DEVICE_HANDLE_LIST_END_KHR 0 + +#endif + +#if !defined(cl_khr_external_memory_opaque_fd) +#define CL_EXTERNAL_MEMORY_HANDLE_OPAQUE_FD_KHR 0x2060 +#endif + +#if !defined(cl_khr_external_memory_win32) +#define CL_EXTERNAL_MEMORY_HANDLE_OPAQUE_WIN32_KHR 0x2061 +#define CL_EXTERNAL_MEMORY_HANDLE_OPAQUE_WIN32_KMT_KHR 0x2062 +#endif + +#if !defined(cl_khr_external_memory_dx) +#define CL_EXTERNAL_MEMORY_HANDLE_D3D11_TEXTURE_KHR 0x2063 +#define CL_EXTERNAL_MEMORY_HANDLE_D3D11_TEXTURE_KMT_KHR 0x2064 +#define CL_EXTERNAL_MEMORY_HANDLE_D3D12_HEAP_KHR 0x2065 +#define CL_EXTERNAL_MEMORY_HANDLE_D3D12_RESOURCE_KHR 0x2066 +#endif + +#if !defined(cl_khr_external_memory_dma_buf) +#define CL_EXTERNAL_MEMORY_HANDLE_DMA_BUF_KHR 0x2067 +#endif + +// cl_intel_variable_eu_thread_count +#define CL_DEVICE_EU_THREAD_COUNTS_INTEL 0x1000A // placeholder +#define CL_KERNEL_EU_THREAD_COUNT_INTEL 0x1000B // placeholder + +#if !defined(cl_intel_maximum_registers) +#define CL_KERNEL_REGISTER_COUNT_INTEL 0x425B +#endif + +/************************************************* + * cl_khr_spirv_queries extension * + *************************************************/ + +#ifndef cl_khr_spirv_queries +#define cl_khr_spirv_queries 1 +#define CL_KHR_SPIRV_QUERIES_EXTENSION_NAME "cl_khr_spirv_queries" +#define CL_DEVICE_SPIRV_EXTENDED_INSTRUCTION_SETS_KHR 0x12B9 +#define CL_DEVICE_SPIRV_EXTENSIONS_KHR 0x12BA +#define CL_DEVICE_SPIRV_CAPABILITIES_KHR 0x12BB +#endif + +/************************************************* + * cl_ext_float_atomics extension * + *************************************************/ + +#if !defined(cl_ext_float_atomics) + +#define cl_ext_float_atomics 1 + +#define CL_DEVICE_SINGLE_FP_ATOMIC_CAPABILITIES_EXT 0x4231 +#define CL_DEVICE_DOUBLE_FP_ATOMIC_CAPABILITIES_EXT 0x4232 +#define CL_DEVICE_HALF_FP_ATOMIC_CAPABILITIES_EXT 0x4233 + +typedef cl_bitfield cl_device_fp_atomic_capabilities_ext; + +#define CL_DEVICE_GLOBAL_FP_ATOMIC_LOAD_STORE_EXT (1 << 0) +#define CL_DEVICE_GLOBAL_FP_ATOMIC_ADD_EXT (1 << 1) +#define CL_DEVICE_GLOBAL_FP_ATOMIC_MIN_MAX_EXT (1 << 2) + +/* bits 3 - 15 are currently unused */ + +#define CL_DEVICE_LOCAL_FP_ATOMIC_LOAD_STORE_EXT (1 << 16) +#define CL_DEVICE_LOCAL_FP_ATOMIC_ADD_EXT (1 << 17) +#define CL_DEVICE_LOCAL_FP_ATOMIC_MIN_MAX_EXT (1 << 18) + +/* bits 19 and beyond are currently unused */ + +#endif + +/************************************************* + * CL_PLATFORM_UNLOADABLE_KHR * + *************************************************/ + +#if !defined(CL_PLATFORM_UNLOADABLE_KHR) +#define CL_PLATFORM_UNLOADABLE_KHR 0x0921 +#endif