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freedreno: fix a few missed afuc -> qrisc renames

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Fixes: 6e3d805735 ("freedreno: Rename afuc to QRisc")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40322>
This commit is contained in:
Eric Engestrom 2026-03-10 13:17:38 +01:00 • committed by Marge Bot
parent b629487a6a
commit 2b7077b8ba
3 changed files with 5 additions and 5 deletions
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2
.mr-label-maker.yml
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@ -162,7 +162,6 @@ merge_requests:
'^src/egl/': ['EGL']
'^src/egl/drivers/wgl/': ['wgl']
'^src/etnaviv/': ['etnaviv']
'^src/freedreno/afuc/': ['freedreno']
'^src/freedreno/common/': ['freedreno']
'^src/freedreno/computerator/': ['freedreno']
'^src/freedreno/decode/': ['freedreno']
@ -174,6 +173,7 @@ merge_requests:
'^src/freedreno/ir3/': ['ir3']
'^src/freedreno/isa/': ['freedreno']
'^src/freedreno/perfcntrs/': ['freedreno']
'^src/freedreno/qrisc/': ['freedreno']
'^src/freedreno/registers/': ['freedreno']
'^src/freedreno/rnn/': ['freedreno']
'^src/freedreno/vulkan/': ['turnip']

6
docs/drivers/freedreno.rst
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@ -54,8 +54,8 @@ Hardware acronyms
SQE
a6xx+ replacement for PFP/ME. This is the microcontroller that runs the
microcode (loaded from Linux) which actually processes the command stream
and writes to the hardware registers. See `afuc
<https://gitlab.freedesktop.org/mesa/mesa/-/blob/main/src/freedreno/afuc/README.rst>`__.
and writes to the hardware registers. See `qrisc
<https://gitlab.freedesktop.org/mesa/mesa/-/blob/main/src/freedreno/qrisc/README.rst>`__.
ROQ
DMA engine used by the SQE for reading memory, with some prefetch buffering.
@ -350,7 +350,7 @@ You would need to disassemble the firmware (/lib/firmware/qcom/aXXX_sqe.fw) via:
.. code-block:: sh
afuc-disasm -v a650_sqe.fw > a650_sqe.fw.disasm
qrisc-disasm -v a650_sqe.fw > a650_sqe.fw.disasm
Now you should search for PC value in the disassembly, e.g.:

2
src/freedreno/registers/adreno/adreno_control_regs.xml
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@ -359,7 +359,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<doc> Controls whether RB, IB1, IB2, IB3, or SDS is executed </doc>
<reg32 name="IB_LEVEL" offset="0x054"/>
<doc> Controls high 32 bits used by load and store afuc instructions </doc>
<doc> Controls high 32 bits used by load and store qrisc instructions </doc>
<reg32 name="LOAD_STORE_HI" offset="0x058"/>
<reg32 name="REG_READ_TEST_RESULT" offset="0x05b">