anv: convert genX_query pipe controls to use pc helper
Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23583>
This commit is contained in:
Tapani Pälli
Marge Bot
parent
d8c76f8844
commit
6dc95685f3
1 changed files with 53 additions and 63 deletions
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@ -674,15 +674,10 @@ emit_ps_depth_count(struct anv_cmd_buffer *cmd_buffer,
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cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
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genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
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pc.DestinationAddressType = DAT_PPGTT;
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pc.PostSyncOperation = WritePSDepthCount;
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pc.DepthStallEnable = true;
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pc.Address = addr;
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if (GFX_VER == 9 && cmd_buffer->device->info->gt == 4)
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pc.CommandStreamerStallEnable = true;
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}
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bool cs_stall_needed = (GFX_VER == 9 && cmd_buffer->device->info->gt == 4);
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genX(batch_emit_pipe_control_write)
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(&cmd_buffer->batch, cmd_buffer->device->info, WritePSDepthCount, addr, 0,
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ANV_PIPE_DEPTH_STALL_BIT | (cs_stall_needed ? ANV_PIPE_CS_STALL_BIT : 0));
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}
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static void
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@ -701,12 +696,9 @@ emit_query_pc_availability(struct anv_cmd_buffer *cmd_buffer,
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cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
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genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
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pc.DestinationAddressType = DAT_PPGTT;
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pc.PostSyncOperation = WriteImmediateData;
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pc.Address = addr;
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pc.ImmediateData = available;
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}
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genX(batch_emit_pipe_control_write)
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(&cmd_buffer->batch, cmd_buffer->device->info, WriteImmediateData, addr,
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available, ANV_PIPE_CS_STALL_BIT);
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}
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/**
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@ -1036,20 +1028,20 @@ void genX(CmdBeginQueryIndexedEXT)(
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break;
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case VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT:
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
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pc.CommandStreamerStallEnable = true;
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pc.StallAtPixelScoreboard = true;
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}
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genX(batch_emit_pipe_control)(&cmd_buffer->batch,
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cmd_buffer->device->info,
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ANV_PIPE_CS_STALL_BIT |
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ANV_PIPE_STALL_AT_SCOREBOARD_BIT);
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mi_store(&b, mi_mem64(anv_address_add(query_addr, 8)),
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mi_reg64(GENX(CL_INVOCATION_COUNT_num)));
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break;
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case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
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/* TODO: This might only be necessary for certain stats */
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
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pc.CommandStreamerStallEnable = true;
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pc.StallAtPixelScoreboard = true;
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}
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genX(batch_emit_pipe_control)(&cmd_buffer->batch,
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cmd_buffer->device->info,
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ANV_PIPE_CS_STALL_BIT |
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ANV_PIPE_STALL_AT_SCOREBOARD_BIT);
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uint32_t statistics = pool->pipeline_statistics;
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uint32_t offset = 8;
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@ -1062,10 +1054,10 @@ void genX(CmdBeginQueryIndexedEXT)(
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}
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case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
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pc.CommandStreamerStallEnable = true;
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pc.StallAtPixelScoreboard = true;
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}
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genX(batch_emit_pipe_control)(&cmd_buffer->batch,
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cmd_buffer->device->info,
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ANV_PIPE_CS_STALL_BIT |
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ANV_PIPE_STALL_AT_SCOREBOARD_BIT);
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emit_xfb_query(&b, index, anv_address_add(query_addr, 8));
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break;
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@ -1121,10 +1113,10 @@ void genX(CmdBeginQueryIndexedEXT)(
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const enum intel_engine_class engine_class = cmd_buffer->queue_family->engine_class;
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mi_self_mod_barrier(&b, devinfo->engine_class_prefetch[engine_class]);
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
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pc.CommandStreamerStallEnable = true;
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pc.StallAtPixelScoreboard = true;
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}
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genX(batch_emit_pipe_control)(&cmd_buffer->batch,
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cmd_buffer->device->info,
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ANV_PIPE_CS_STALL_BIT |
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ANV_PIPE_STALL_AT_SCOREBOARD_BIT);
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cmd_buffer->perf_query_pool = pool;
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cmd_buffer->perf_reloc_idx = 0;
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@ -1183,10 +1175,10 @@ void genX(CmdBeginQueryIndexedEXT)(
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}
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case VK_QUERY_TYPE_PERFORMANCE_QUERY_INTEL: {
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
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pc.CommandStreamerStallEnable = true;
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pc.StallAtPixelScoreboard = true;
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}
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genX(batch_emit_pipe_control)(&cmd_buffer->batch,
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cmd_buffer->device->info,
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ANV_PIPE_CS_STALL_BIT |
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ANV_PIPE_STALL_AT_SCOREBOARD_BIT);
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emit_perf_intel_query(cmd_buffer, pool, &b, query_addr, false);
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break;
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}
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@ -1230,10 +1222,10 @@ void genX(CmdEndQueryIndexedEXT)(
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/* Ensure previous commands have completed before capturing the register
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* value.
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*/
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
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pc.CommandStreamerStallEnable = true;
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pc.StallAtPixelScoreboard = true;
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}
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genX(batch_emit_pipe_control)(&cmd_buffer->batch,
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cmd_buffer->device->info,
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ANV_PIPE_CS_STALL_BIT |
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ANV_PIPE_STALL_AT_SCOREBOARD_BIT);
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mi_store(&b, mi_mem64(anv_address_add(query_addr, 16)),
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mi_reg64(GENX(CL_INVOCATION_COUNT_num)));
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@ -1242,10 +1234,10 @@ void genX(CmdEndQueryIndexedEXT)(
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case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
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/* TODO: This might only be necessary for certain stats */
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
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pc.CommandStreamerStallEnable = true;
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pc.StallAtPixelScoreboard = true;
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}
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genX(batch_emit_pipe_control)(&cmd_buffer->batch,
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cmd_buffer->device->info,
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ANV_PIPE_CS_STALL_BIT |
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ANV_PIPE_STALL_AT_SCOREBOARD_BIT);
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uint32_t statistics = pool->pipeline_statistics;
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uint32_t offset = 16;
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@ -1260,20 +1252,19 @@ void genX(CmdEndQueryIndexedEXT)(
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}
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case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
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pc.CommandStreamerStallEnable = true;
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pc.StallAtPixelScoreboard = true;
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}
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genX(batch_emit_pipe_control)(&cmd_buffer->batch,
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cmd_buffer->device->info,
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ANV_PIPE_CS_STALL_BIT |
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ANV_PIPE_STALL_AT_SCOREBOARD_BIT);
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emit_xfb_query(&b, index, anv_address_add(query_addr, 16));
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emit_query_mi_availability(&b, query_addr, true);
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break;
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case VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR: {
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
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pc.CommandStreamerStallEnable = true;
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pc.StallAtPixelScoreboard = true;
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}
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genX(batch_emit_pipe_control)(&cmd_buffer->batch,
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cmd_buffer->device->info,
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ANV_PIPE_CS_STALL_BIT |
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ANV_PIPE_STALL_AT_SCOREBOARD_BIT);
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cmd_buffer->perf_query_pool = pool;
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if (!khr_perf_query_ensure_relocs(cmd_buffer))
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@ -1348,10 +1339,10 @@ void genX(CmdEndQueryIndexedEXT)(
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}
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case VK_QUERY_TYPE_PERFORMANCE_QUERY_INTEL: {
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
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pc.CommandStreamerStallEnable = true;
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pc.StallAtPixelScoreboard = true;
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}
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genX(batch_emit_pipe_control)(&cmd_buffer->batch,
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cmd_buffer->device->info,
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ANV_PIPE_CS_STALL_BIT |
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ANV_PIPE_STALL_AT_SCOREBOARD_BIT);
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uint32_t marker_offset = intel_perf_marker_offset();
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mi_store(&b, mi_mem64(anv_address_add(query_addr, marker_offset)),
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mi_imm(cmd_buffer->intel_perf_marker));
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@ -1412,14 +1403,13 @@ void genX(CmdWriteTimestamp2)(
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cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
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genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
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pc.DestinationAddressType = DAT_PPGTT;
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pc.PostSyncOperation = WriteTimestamp;
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pc.Address = anv_address_add(query_addr, 8);
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bool cs_stall_needed =
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(GFX_VER == 9 && cmd_buffer->device->info->gt == 4);
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genX(batch_emit_pipe_control_write)
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(&cmd_buffer->batch, cmd_buffer->device->info, WriteTimestamp,
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anv_address_add(query_addr, 8), 0,
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cs_stall_needed ? ANV_PIPE_CS_STALL_BIT : 0);
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if (GFX_VER == 9 && cmd_buffer->device->info->gt == 4)
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pc.CommandStreamerStallEnable = true;
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}
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emit_query_pc_availability(cmd_buffer, query_addr, true);
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}
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