dsg/mesa
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

brw: Simplify GS load_invocation_id handling

Browse source 
Just return the register instead of having multiple functions stash the
register in an array of registers.  Way too much hoopla here.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40328>
This commit is contained in:
Kenneth Graunke 2026-03-06 17:36:13 -08:00 • committed by Marge Bot
parent 9933882182
commit 7d463a45f7
1 changed files with 2 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

18
src/intel/compiler/brw/brw_from_nir.cpp
View file

@ -134,16 +134,6 @@ emit_system_values_block(nir_to_brw_state &ntb, nir_block *block)
UNREACHABLE("should be lowered by brw_nir_lower_vs_inputs().");
break;
case nir_intrinsic_load_invocation_id:
if (s.stage == MESA_SHADER_TESS_CTRL)
break;
assert(s.stage == MESA_SHADER_GEOMETRY);
reg = &ntb.system_values[SYSTEM_VALUE_INVOCATION_ID];
if (reg->file == BAD_FILE) {
*reg = s.gs_payload().instance_id;
}
break;
case nir_intrinsic_load_sample_pos:
case nir_intrinsic_load_sample_pos_or_center:
assert(s.stage == MESA_SHADER_FRAGMENT);
@ -3102,13 +3092,9 @@ brw_from_nir_emit_gs_intrinsic(nir_to_brw_state &ntb,
bld.MOV(s.final_gs_vertex_count, get_nir_src(ntb, instr->src[0], 0));
break;
case nir_intrinsic_load_invocation_id: {
brw_reg val = ntb.system_values[SYSTEM_VALUE_INVOCATION_ID];
assert(val.file != BAD_FILE);
dest.type = val.type;
bld.MOV(dest, val);
case nir_intrinsic_load_invocation_id:
bld.MOV(dest, retype(s.gs_payload().instance_id, dest.type));
break;
}
default:
brw_from_nir_emit_intrinsic(ntb, bld, instr);