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brw: prevent LOAD_REG modifications on MOV_INDIRECT/BROADCAST

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Due to those opcode reading variable amount of data in src0, it's not
possible to easily figure out what builder SIMD size should be used to
produce the LOAD_REG replacement.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 2d13acf9d9 ("brw: Add passes to generate and lower load_reg")
Fixes: 93996c07e2 ("brw: fix broadcast opcode")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14054
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37756>
This commit is contained in:
Lionel Landwerlin 2025-10-08 09:00:15 +03:00 • committed by Marge Bot
parent a21b925caa
commit acf953757e
1 changed files with 9 additions and 4 deletions
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13
src/intel/compiler/brw_load_reg.cpp
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@ -27,12 +27,17 @@ brw_insert_load_reg(brw_shader &s)
/* These should not exist yet. */
assert(inst->opcode != SHADER_OPCODE_LOAD_REG);
/* These opcodes may have the right source and destination patterns to
* have their sources replaced by load_reg, but these instructions are
* special and / or wierd. They should not be modified.
/* UNDEF/DPAS opcodes may have the right source and destination patterns
* to have their sources replaced by load_reg, but these instructions
* are special and / or wierd. They should not be modified.
*
* MOV_INDIRECT/BROADCAST read variable amount of GRF for src0. This
* pass does not handle this properly at the moment.
*/
if (inst->opcode == SHADER_OPCODE_UNDEF ||
inst->opcode == BRW_OPCODE_DPAS) {
inst->opcode == BRW_OPCODE_DPAS ||
inst->opcode == SHADER_OPCODE_MOV_INDIRECT ||
inst->opcode == SHADER_OPCODE_BROADCAST) {
continue;
}