Commit graph

220215 commits

Author SHA1 Message Date
Georg Lehmann
cf4182ef5e broadcom/ci: skip rpi4 timeout
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40399>
2026-03-20 08:50:41 +00:00
Georg Lehmann
643dd510d4 nir/opt_algebraic: optimize b2f(a) * b
When the multiplication is only used by fadd, it's not a clear win
because of potential fma fusion.

Totals from 8015 (6.99% of 114655) affected shaders:
MaxWaves: 199394 -> 199466 (+0.04%); split: +0.04%, -0.01%
Instrs: 17461518 -> 17451076 (-0.06%); split: -0.10%, +0.04%
CodeSize: 94779552 -> 94769828 (-0.01%); split: -0.07%, +0.06%
VGPRs: 526012 -> 525532 (-0.09%); split: -0.10%, +0.01%
SpillSGPRs: 12466 -> 12517 (+0.41%); split: -0.09%, +0.50%
Latency: 191274766 -> 191297394 (+0.01%); split: -0.03%, +0.04%
InvThroughput: 31465968 -> 31456785 (-0.03%); split: -0.07%, +0.04%
VClause: 312081 -> 312073 (-0.00%); split: -0.10%, +0.09%
SClause: 366914 -> 366906 (-0.00%); split: -0.02%, +0.01%
Copies: 1222482 -> 1221933 (-0.04%); split: -0.20%, +0.15%
Branches: 376651 -> 376577 (-0.02%); split: -0.03%, +0.01%
PreSGPRs: 442974 -> 443240 (+0.06%); split: -0.01%, +0.07%
PreVGPRs: 415964 -> 415668 (-0.07%); split: -0.09%, +0.02%
VALU: 9403517 -> 9393916 (-0.10%); split: -0.12%, +0.02%
SALU: 2799420 -> 2800430 (+0.04%); split: -0.13%, +0.16%
VOPD: 472826 -> 472347 (-0.10%); split: +0.09%, -0.19%

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40399>
2026-03-20 08:50:41 +00:00
Georg Lehmann
d2b37b667e nir/opt_algebraic: optimize more fmulz(1.0, a) remains
If dxvk's opencoded fmulz gets partially constant folded,
it leaves this mess behind.

It's important to do this before the more general fmul+b2f patterns added
in the next commit, because they change the signed zero behavior in a way
that can't be optimized back.

Foz-DB Navi48:
Totals from 36 (0.03% of 114655) affected shaders:

Instrs: 16513 -> 15706 (-4.89%)
CodeSize: 99756 -> 95760 (-4.01%)
Latency: 45165 -> 44151 (-2.25%)
InvThroughput: 8344 -> 7886 (-5.49%)
VClause: 395 -> 401 (+1.52%)
Copies: 639 -> 634 (-0.78%)
PreSGPRs: 1158 -> 1154 (-0.35%)
PreVGPRs: 1227 -> 1225 (-0.16%)
VALU: 11310 -> 10769 (-4.78%)
SALU: 813 -> 809 (-0.49%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40399>
2026-03-20 08:50:41 +00:00
Georg Lehmann
3ad142d4d7 nir/search: never insert movs for alu uses
This means we respect the pattern order better because
simple replacements like bcsel(False, a, b) -> b no longer
insert movs that can block more specialized patterns.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40399>
2026-03-20 08:50:41 +00:00
Georg Lehmann
1626df7a90 nir: rework nir_alu_src_is_trivial_ssa to take an alu src
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40399>
2026-03-20 08:50:41 +00:00
Georg Lehmann
b96c42c916 nir/opt_algebraic: optimize more near useless bcsel
Foz-DB Navi48:
Totals from 327 (0.29% of 114655) affected shaders:
Instrs: 732971 -> 731642 (-0.18%); split: -0.19%, +0.01%
CodeSize: 3696020 -> 3689824 (-0.17%); split: -0.17%, +0.00%
Latency: 4405319 -> 4403413 (-0.04%); split: -0.06%, +0.01%
InvThroughput: 650209 -> 649659 (-0.08%); split: -0.10%, +0.01%
Copies: 53872 -> 53736 (-0.25%); split: -0.27%, +0.02%
Branches: 15598 -> 15571 (-0.17%)
VALU: 262391 -> 261969 (-0.16%)
SALU: 268112 -> 267699 (-0.15%)

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40399>
2026-03-20 08:50:41 +00:00
Georg Lehmann
6cfe6eaa79 nir/opt_algebraic: create ldexp from exp2
ldexp uses the full width VALU path, exp2 the transcendental SIMD8.

Foz-DB Navi21:
Totals from 729 (0.64% of 114627) affected shaders:
MaxWaves: 20071 -> 20103 (+0.16%); split: +0.18%, -0.02%
Instrs: 869129 -> 867654 (-0.17%); split: -0.17%, +0.00%
CodeSize: 4709000 -> 4708460 (-0.01%); split: -0.02%, +0.00%
VGPRs: 31184 -> 31128 (-0.18%); split: -0.23%, +0.05%
Latency: 7610726 -> 7597238 (-0.18%); split: -0.18%, +0.00%
InvThroughput: 1822323 -> 1819815 (-0.14%); split: -0.14%, +0.00%
VClause: 22494 -> 22493 (-0.00%); split: -0.03%, +0.02%
SClause: 20520 -> 20509 (-0.05%)
Copies: 72025 -> 72024 (-0.00%); split: -0.01%, +0.01%
Branches: 22028 -> 22029 (+0.00%)
PreVGPRs: 21601 -> 21602 (+0.00%)
VALU: 604821 -> 603339 (-0.25%); split: -0.25%, +0.00%
SALU: 114258 -> 114262 (+0.00%); split: -0.00%, +0.01%

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33900>
2026-03-20 08:15:08 +00:00
Georg Lehmann
ec331cc48a nir: replace lower_ldexp with has_ldexp
I can be bothered to fix all the backends that don't set lower_ldexp,
and only two backends have ldexp anyway.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33900>
2026-03-20 08:15:08 +00:00
Iván Briano
fd556e54f6 brw: do not omit RT writes if dual_src_blend is on
Dual source blending when one of the sources is not written to leaves
those values undefined, but the other should still be valid.
By omitting unwritten outputs, we ended up not writing anything at all
for the case that OUT1 is written to but OUT0 is undefined.

Fixes new CTS tests: dEQP-VK.pipeline.*.blend.dual_source.undefined_output.first*

Cc: mesa-stable
Signed-off-by: Iván Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40357>
2026-03-19 23:38:40 +00:00
Iván Briano
2ce8a9e1be anv: fix anv_is_dual_src_blend_equation
Fixes new tests: dEQP-VK.pipeline.*.blend.dual_source.undefined_output.second*

Cc: mesa-stable
Signed-off-by: Iván Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40357>
2026-03-19 23:38:40 +00:00
Tapani Pälli
8afb28952c intel/dev: update mesa_defs.json from workaround database
This bring NVL_U workarounds and one update for PTL and WCL.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/15067
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40508>
2026-03-19 20:58:37 +00:00
Tapani Pälli
9384fd42f9 intel/dev: add NVL_U, NVL_P platforms to gen_wa_helpers.py
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40508>
2026-03-19 20:58:37 +00:00
Danylo Piliaiev
b86ecec80b tu: Fix imported memory not being affected by DEVICE_ADDRESS_CAPTURE_REPLAY
It's valid to import memory with DEVICE_ADDRESS_CAPTURE_REPLAY_BIT
and we should allocate iova from the end of VMA heap, same as with ordinary
memory allocations. This is important for replaying such memory, when it
is being replayed without being imported.

Fixes replay errors with RenderDoc.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40378>
2026-03-19 20:28:39 +00:00
Rob Clark
48be91d14b freedreno/common: Fix upstream a830 chip_id
Add missing fuse bits (which are all `1` if no fuse).

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40458>
2026-03-19 19:58:20 +00:00
Rob Clark
55ee6aa57c freedreno/a6xx: Move A2D reg write to ncrb
It is not a 3d context reg.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40458>
2026-03-19 19:58:20 +00:00
Samuel Pitoiset
130a066d58 radv: stop passing radv_device for creating NIR meta shaders
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40481>
2026-03-19 19:23:55 +00:00
Samuel Pitoiset
6bf978e13e radv: move setting NIR options for meta shaders
To remove radv_device from radv_meta_nir_init_shader().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40481>
2026-03-19 19:23:55 +00:00
Samuel Pitoiset
dcf0274e82 radv: stop associating NIR with device for debugging tools
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40481>
2026-03-19 19:23:55 +00:00
Samuel Pitoiset
fddbeddb2d radv: move valid VA debug info to radv_valid_va data
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40481>
2026-03-19 19:23:54 +00:00
Samuel Pitoiset
7ce3b2a68e radv: move radv_printf_data to radv_debug_nir
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40481>
2026-03-19 19:23:54 +00:00
Samuel Pitoiset
f776a763b4 radv: remove unnecessary radv_device parameter to few functions
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40481>
2026-03-19 19:23:54 +00:00
Samuel Pitoiset
59883a5cb6 vulkan: stop passing vk_device to vk_set_subgroup_size()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40481>
2026-03-19 19:23:54 +00:00
Silvio Vilerino
6e39982b32 d3d12: d3d12_video_encode_support_caps was assigning a stack variable address to capEncoderSupportData in/out arg
Reviewed-by: Pohsiang (John) Hsu <pohhsu@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40511>
2026-03-19 19:06:51 +00:00
Silvio Vilerino
0e37a80aca d3d12: Truncate move_rects_support.bits.max_motion_hints 16 bit var to 65535, not 65536
Reviewed-by: Pohsiang (John) Hsu <pohhsu@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40511>
2026-03-19 19:06:51 +00:00
Pohsiang (John) Hsu
d2ad51fc0a mediafoundation: set reasonable number of reference frames if the user didn't set CODECAPI_AVEncVideoMaxNumRefFrame
Reviewed-by: Yubo Xie <yuboxie@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40511>
2026-03-19 19:06:51 +00:00
Pohsiang (John) Hsu
c97ff97df6 mediafoundation: set defualt unwrapped poc for h264 to true
Reviewed-by: Yubo Xie <yuboxie@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40511>
2026-03-19 19:06:51 +00:00
Pohsiang (John) Hsu
7ae3977fe7 mediafoundation: fix hevc vui time_scale
Reviewed-by: Yubo Xie <yuboxie@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40511>
2026-03-19 19:06:51 +00:00
Thong Thai
525fcdfcee radeonsi: remove radeonsi prefix from si_pipe.h includes
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40518>
2026-03-19 18:47:29 +00:00
Lionel Landwerlin
5d7cf5e762 anv: don't queue pipe control reasons wihout a trace
When there is no trace pointer, there is usually a another tracepoint
being emitted (see STATE_BASE_ADDRESS,
3DSTATE_BINDING_TABLE_POOL_ALLOC emission).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40503>
2026-03-19 18:13:46 +00:00
Ian Romanick
d038bfa1c1 util: Use same method to clear bits in u_foreach_bit as util_bitcount
Saves about 2k text size.

Before:

   text	   data	    bss	    dec	    hex	filename
24817485	 456164	  27080	25300729	1820ef9	./lib64/libvulkan_intel.so

After:

   text	   data	    bss	    dec	    hex	filename
24815381	 456164	  27080	25298625	18206c1	./lib64/libvulkan_intel.so

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40230>
2026-03-19 17:30:25 +00:00
Ian Romanick
e13565acf4 anv: Use u_foreach_bit
Suggested-by: Lionel
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40230>
2026-03-19 17:30:25 +00:00
Ian Romanick
4cbf2ee3f0 anv: Use different logic to isolate lowest flag in anv_foreach_vk_stage
Silences many ubsan errors like:

src/intel/vulkan/anv_shader_compile.c:609:4: runtime error: shift exponent -1 is negative

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40230>
2026-03-19 17:30:25 +00:00
Anders Roxell
ea731cda12 ethosu: fix blockdep to check for data dependencies
calc_blockdep always returned MAX_BLOCKDEP without checking if the
previous op writes to a buffer the current op reads from. This let
the NPU start reading before the previous write was done.

Add overlap check between previous OFM and current IFM so we set
blockdep to 0 when they share the same buffer.

Update ethos-imx93-fails.txt to remove the tests that now pass.

Signed-off-by: Anders Roxell <anders.roxell@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39594>
2026-03-19 16:43:13 +00:00
Anders Roxell
17435b6a58 teflon/tests: add micronet_large anomaly detection model
Downloaded from the Arm ML Zoo [1]. Per-channel quantized INT8 model
with 14 operators: CONV_2D (7x), DEPTHWISE_CONV_2D (5x),
AVERAGE_POOL_2D, RESHAPE. All per-op tests pass but the full model
fails due to a bug in synchronization of operations.

[1] https://github.com/Arm-Examples/ML-zoo/tree/master/models/anomaly_detection/micronet_large/tflite_int8

Signed-off-by: Anders Roxell <anders.roxell@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39594>
2026-03-19 16:43:13 +00:00
Anders Roxell
7c1ec56427 ethosu: clean up ADD elementwise scaling
Replace the two functions simplified_elementwise_add_sub_scale and
eltwise_emit_ofm_scaling with a single advanced_elementwise_add_sub_scale
that follows the ethos-u-vela naming. Remove the large block of
commented out Vela Python code.

No functional change.

Signed-off-by: Anders Roxell <anders.roxell@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39594>
2026-03-19 16:43:13 +00:00
Anders Roxell
69d3f080be ethosu: fix RESIZE upscale mode
The upscale field was a bool which happened to work since true maps
to 1 which is NEAREST in the hardware. Change from bool to an enum
ethosu_upscale_mode so the intent is clear and we dont rely on the
bool-to-int mapping.

Also add a check in operation_supported so RESIZE only accepts 2x
upscaling since thats what the NPU can do with IFM_UPSCALE. Other
sizes fall back to CPU.

Keep the original zero_points from tensors in RESIZE and STRIDED_SLICE
instead of forcing them to 0 since the requantization needs them.

Fixes the RESIZE_NEAREST_NEIGHBOR operations in EfficientDet-Lite
models that use BiFPN with 2x nearest neighbor upsampling.

Signed-off-by: Anders Roxell <anders.roxell@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39594>
2026-03-19 16:43:12 +00:00
Anders Roxell
e27ba5b437 ethosu: Handle per-channel zero_points
fill_weights subtracted a single zero_point from all weights which
did not handle models with per-channel zero_points. Use the
per-channel zero_point for each output channel when available.

Also decouple the zero_points copy from the scales copy in the lower
pass so they are handled independently.

Suggested-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Signed-off-by: Anders Roxell <anders.roxell@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39594>
2026-03-19 16:43:12 +00:00
Anders Roxell
63c028b5e0 ethosu: Add support for per-channel quantization
For those models with coefficients that have different quantization
parameters for each channel.

The NPU can handle per-channel scales as can be seen in
fill_scale_and_biases(), which already iterates per output channel.

Activation tensors (input/output) don't have per-channel quantization.

- Add scales/zero_points arrays to ethosu_kernel struct
- Copy per-channel scales from weight tensor in lower pass
- Use per-channel scale when computing conv_scale in coefs
- Allow per-channel quantization in operation_supported check

Signed-off-by: Anders Roxell <anders.roxell@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39594>
2026-03-19 16:43:12 +00:00
Anders Roxell
0887e6d89f teflon: Add support for symmetric per-channel quantization
The old code would assert when a model has multiple scales but only
one zero_point. This is common for symmetric quantization where all
channels share the same zero_point (typically 0).

Handle this by replicating the single zero_point for all channels
instead of crashing.

Fixes MoveNet models using per-channel quantization.

Signed-off-by: Anders Roxell <anders.roxell@linaro.org>
Reviewed-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39594>
2026-03-19 16:43:11 +00:00
Lars-Ivar Hesselberg Simonsen
292fffac1b pan/va/disasm: Move src discard marker behind reg
Purely a visual change, but aligns with DDK disassembly.

For example:
-   FMA.f32 r1, ^r1, u1, ^r4
+   FMA.f32 r1, r1^, u1, r4^

Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Acked-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40199>
2026-03-19 15:11:13 +00:00
Lars-Ivar Hesselberg Simonsen
43c6f51a29 pan/va/disasm: Clean up hardcoded values
A lot of masks and shifts were hard-coded in the disassembler. This
commit tries to move them to shared logic.

Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Acked-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40199>
2026-03-19 15:11:13 +00:00
Lars-Ivar Hesselberg Simonsen
614d07c986 pan/va: Generalize opcode/opcode2
Rather than opcode/opcode2 hardcoded, treat the opcode as a list of
one or more subcodes.

This implies modifying the disassembler to hold an arbitrary depth dict
of dicts and recursively build the switch statements used to look up
each level.

Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Acked-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40199>
2026-03-19 15:11:13 +00:00
Lars-Ivar Hesselberg Simonsen
11f243205c pan/va/disasm: Move instr print to function
This splits the printing logic from the iteration logic, making it
easier to reason about either.

Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Acked-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40199>
2026-03-19 15:11:12 +00:00
Lars-Ivar Hesselberg Simonsen
adffad6adb pan/va: XMLify opcode2
Opcode2 was a bit all over the place, so utilize the new opcode modifier
to gather opcode2 information in a single place.

This cleans up the implicit va_mods "left", "descriptor_type" and
"memory_width".

Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Acked-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40199>
2026-03-19 15:11:12 +00:00
Lars-Ivar Hesselberg Simonsen
5b24568c87 pan/va: Add opcode modifier to ISA.xml
Rather than having the opcode as an attribute and the offset/mask being
implicit, make all of this information explicit in the xml.

Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Acked-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40199>
2026-03-19 15:11:12 +00:00
Lars-Ivar Hesselberg Simonsen
9bd4a40233 pan/va: Clean up unused/removed instructions
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Acked-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40199>
2026-03-19 15:11:12 +00:00
Lars-Ivar Hesselberg Simonsen
1b1f4bd35e pan/va: Remove non-existent unused CLPERs
These instructions were not generated as they do not exist.

Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Acked-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40199>
2026-03-19 15:11:12 +00:00
Eric Engestrom
384d128164 ci: fix scheduled pipelines
Fixes: 32a818d11d ("ci: drop workaround for jobs not being created in fork pipelines")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40505>
2026-03-19 13:23:00 +00:00
Eric Engestrom
d38916d673 ci: fix rebase mistake
Fixes: 32a818d11d ("ci: drop workaround for jobs not being created in fork pipelines")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40505>
2026-03-19 13:23:00 +00:00
Erik Faye-Lund
982f567b19 pan/lib: drop redundant assign
This is already the default value, so there's no point in overriding it
to itself.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40489>
2026-03-19 12:00:47 +00:00