arch: Mask (out) extended AMX features
The Intel Granite Rapids processors include more AMX related features that are advertised in leaf 0x7 subleaf 0x1. If the VM is not configured to support AMX (the default) then these feature bits need to be masked out. Furthermore Tile information and TMUL information in leaves 0x1d and 0x1e respectively are also purely related to AMX and should also be zeroed whenever AMX support is disabled. Signed-off-by: Oliver Anderson <oliver.anderson@cyberus-technology.de> On-behalf-of: SAP <oliver.anderson@sap.com>
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1 changed files with 30 additions and 2 deletions
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@ -50,6 +50,9 @@ const AMX_BF16: u8 = 22; // AMX tile computation on bfloat16 numbers
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const AMX_TILE: u8 = 24; // AMX tile load/store instructions
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const AMX_INT8: u8 = 25; // AMX tile computation on 8-bit integers
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const AMX_FP16: u8 = 21; // AMX tile computation on fp16 numbers
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const AMX_COMPLEX: u8 = 8; // AMX tile computation on complex numbers
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// KVM feature bits
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#[cfg(feature = "tdx")]
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const KVM_FEATURE_CLOCKSOURCE_BIT: u8 = 0;
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@ -638,8 +641,14 @@ pub fn generate_common_cpuid(
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match entry.function {
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// Clear AMX related bits if the AMX feature is not enabled
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0x7 => {
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if !config.amx && entry.index == 0 {
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entry.edx &= !((1 << AMX_BF16) | (1 << AMX_TILE) | (1 << AMX_INT8));
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if !config.amx {
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if entry.index == 0 {
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entry.edx &= !((1 << AMX_BF16) | (1 << AMX_TILE) | (1 << AMX_INT8));
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}
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if entry.index == 1 {
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entry.eax &= !(1 << AMX_FP16);
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entry.edx &= !(1 << AMX_COMPLEX);
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}
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}
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}
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0xd =>
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@ -661,6 +670,25 @@ pub fn generate_common_cpuid(
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}
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}
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}
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0x1d => {
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// Tile Information (purely AMX related).
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if !config.amx {
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entry.eax = 0;
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entry.ebx = 0;
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entry.ecx = 0;
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entry.edx = 0;
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}
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}
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0x1e => {
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// TMUL information (purely AMX related)
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if !config.amx {
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entry.eax = 0;
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entry.ebx = 0;
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entry.ecx = 0;
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entry.edx = 0;
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}
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}
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// Copy host L1 cache details if not populated by KVM
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0x8000_0005 => {
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if entry.eax == 0 && entry.ebx == 0 && entry.ecx == 0 && entry.edx == 0 {
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