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Jinank Jain 7fd1b9a284 hypervisor: Configure VGIC for MSHV guests 
As part of this configuration, two things are being done:

1. Setting up the base address of GIC Distributor
2. Setting up the base address of GIC Interrupt Translator

Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
2025-04-23 07:42:29 +00:00
..
arch hypervisor: Refactor common PSTATE register definition 2025-04-23 07:42:29 +00:00
kvm hypervisor: Refactor common PSTATE register definition 2025-04-23 07:42:29 +00:00
mshv hypervisor: Configure VGIC for MSHV guests 2025-04-23 07:42:29 +00:00
cpu.rs hypervisor, vmm: Avoid leaking hypervisor specific data structure 2025-02-12 23:08:43 +00:00
device.rs hypervisor, vmm: use new vfio-ioctls 2022-07-21 23:37:53 +01:00
hypervisor.rs hypervisor: use memory size during VM creation 2024-12-12 03:32:22 +00:00
lib.rs hypervisor: Enable MSHV compilation on ARM64 2025-04-16 03:36:12 +00:00
vm.rs hypervisor: Implement hypervisor agnostic variant of VcpuInit 2025-02-12 23:08:43 +00:00